bi-CMOS buffer cascaded to CMOS driver having PMOS pull-up trans

Details bi-CMOS buffer cascaded to CMOS driver having PMOS pull-up trans bi-CMOS buffer cascaded to CMOS driver having PMOS pull-up trans

1987-09-02

1989-02-21

Hudspeth, David

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307443, 307451, 307362, 307570, H03K 1716, H03K 1756

Patent

active

048067970

ABSTRACT:
For reduction in power consumption, there is disclosed a buffer circuit for a subsequent stage having a CMOS inverter circuit with a preselected threshold voltage coupled between a positive voltage source and a source of ground voltage comprising an input node to which an input signal appears, an output node coupled to the gate electrodes of the CMOS inverter circuit, and a n-p-n type bipolar transistor having a base electrode coupled to the input node, an emitter electrode coupled to the output node and a collector electrode coupled to the source of positive voltage, the bipolar transistor provides a conduction path from the source of positive voltage to the output node when the bipolar transistor is turned on, and the output node is electrically connected to the source of ground voltage when the bipolar transistor is turned off, wherein the bipolar transistor turns on in the presence of a preselected difference voltage between the emitter electrode and the base electrode and the preselected difference voltage is smaller in value than the preselected threshold voltage, so that the CMOS inverter circuit is prevented from a conduction path passing therethrough.

REFERENCES:
patent: 4301383 (1981-11-01), Taylor
patent: 4682054 (1987-07-01), McLaughlin
patent: 4694202 (1987-09-01), Iwamura et al.
patent: 4694203 (1987-09-01), Uragami et al.
patent: 4701642 (1987-10-01), Pricer
patent: 4730132 (1988-03-01), Watanabe et al.

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