BGA package with stacked semiconductor chips and method of...

Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Assembly of plural semiconductive substrates each possessing...

Reexamination Certificate

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C257S686000, C257SE23085

Reexamination Certificate

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10850154

ABSTRACT:
A package with two or more stacked semiconductor chips and a method of manufacturing the same. In the method, an upper semiconductor chip package and a lower semiconductor chip package are prepared. Solder balls are formed on a substrate of the lower package to connect the upper and lower packages. A semiconductor chip and the solder balls are molded and then ground until the solder balls are exposed. Solder balls are formed on the bottom of a substrate of the upper package. The upper package is stacked on the lower package such that the solder balls of the lower package are in contact with the solder balls of the upper package. A reflow process is performed on the lower package and the upper package, which are stacked, to physically connect the upper and lower packages.

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patent: 6451626 (2002-09-01), Lin
patent: 6548330 (2003-04-01), Murayama et al.
patent: 6740546 (2004-05-01), Corisis et al.
patent: 7071028 (2006-07-01), Koike et al.
patent: 2002/0000648 (2002-01-01), Leong et al.
patent: 2002/0135057 (2002-09-01), Kurita
patent: 1999-0086915 (1999-12-01), None
patent: 010056937 (2001-07-01), None
patent: 2002-0043435 (2002-06-01), None

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