Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package
Reexamination Certificate
2000-03-21
2002-10-29
Enad, Elvin (Department: 2832)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
C257S737000, C257S787000, C438S106000, C438S121000
Reexamination Certificate
active
06472732
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATION
This application claims the priority of Application No. H11-302497, filed Oct. 25, 1999 in Japan, the subject matter of which is incorporated herein by reference.
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a BGA (Ball Grid Array) package, and a method for fabricating the same.
BACKGROUND OF THE INVENTION
A conventional BGA package includes a substrate having a copper plate. an insulating layer and a copper wiring pattern. The BGA package is designed to have a good characteristic of heat radiation. The insulating layer may be of polyimide, which is formed on the copper plate. The copper wiring pattern is formed on the insulating layer. The substrate is provided with solder balls to be connected to a motherboard. A semiconductor chip is connected at electrodes to the copper wiring pattern by bonding wires.
According to the above described conventional BGA package, when a large number of solder balls are used or the solder balls are arranged with a smaller pitch, some of the solder balls are not used for operation. In other words, a large number of excess or redundant terminals are made. Such excess terminals are not electrically connected to the semiconductor chip. Further, when the conventional BGA package with a large number of solder balls is mounted on a motherboard, the BGA package occupies a larger area on the motherboard. As a result, the motherboard would be larger in size.
OBJECTS OF THE INVENTION
Accordingly, an object of the present invention is to provide a ball grid array (BGA) package in which solder balls are used efficiently without making a large number of excess terminals (solder balls). This feature allows that a BGA package can be fabricated small in size with higher integration.
Another object of the present invention is to provide a method for fabricating a ball grid array (BGA) package in which solder balls are used efficiently without making a large number of excess terminals (solder balls). This feature allows that a BGA package can be fabricated small in size with higher integration.
Additional objects, advantages and novel features of the present invention will be set forth in part in the description that follows, and in part will become apparent to those skilled in the art upon examination of the following or may be learned by practice of the invention. The objects and advantages of the invention may be realized and attained by means of the instrumentalities and combinations particularly pointed out in the appended claims.
SUMMARY OF THE INVENTION
According to a first aspect of the present invention, a ball grid array (BGA) package includes a substrate (
20
) having first and second surfaces, and through holes (
30
) passing through it. The package further includes a first semiconductor chip (
28
) which is mounted on the first surface of the substrate (
20
); a second semiconductor chip (
36
) which is mounted on the second surface of the substrate (
20
); and solder balls (
34
) which are provided on the first surface of the substrate (
20
) and are electrically connected to the first semiconductor chip (
28
). The second semiconductor chip (
36
) is electrically connected via the through holes (
30
) to the solder balls (
34
).
According to a second aspect of the present invention, a method includes the steps of providing a substrate (
20
) having first and second surfaces, and through holes (
30
) passing through it; mounting a first semiconductor chip (
28
) on the first surface of the substrate (
20
); and mounting a second semiconductor chip (
36
) on the second surface of the substrate (
20
). The method further includes the step of providing solder balls (
34
) on the first surface of the substrate (
20
) so that the solder balls (
34
) are electrically connected to the first semiconductor chip (
28
) and to the second semiconductor chip (
36
) via the through holes (
30
).
REFERENCES:
patent: 5239198 (1993-08-01), Lin et al.
patent: 5798564 (1998-08-01), Eng et al.
patent: 5869889 (1999-02-01), Chia et al.
patent: 5870289 (1999-02-01), Tokuda et al.
patent: 5900675 (1999-05-01), Appelt et al.
patent: 5977633 (1999-11-01), Suzuki et al.
patent: 6229215 (2001-05-01), Egawa
patent: 6232667 (2001-05-01), Hultmark et al.
Enad Elvin
Lee Kyung S.
Oki Electric Industry Co. Ltd.
Rabin & Berdo
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