Bell jar having integral gas distribution channeling

Coating apparatus – Gas or vapor deposition

Reexamination Certificate

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Details

C118S724000, C432S241000

Reexamination Certificate

active

06302963

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to the field of thermal processing systems, and more particularly to an improved thermal process chamber for a vertical thermal processing system having integral gas distribution channels.
BACKGROUND OF THE INVENTION
Thermal processing furnaces have been widely known and used for many years to perform a variety of semiconductor fabrication processes, including annealing, diffusion, oxidation, and chemical vapor deposition (CVD) processes. As a result, these processes are well understood, especially with regard to the impact of process variables on the quality and uniformity of resulting products. Thermal processing systems typically employ either a horizontal-type or vertical-type furnace. For some applications, vertical-type furnaces are preferred because they create less particles during use, thus decreasing the incidence of contamination and wafer waste, they can be easily automated, and they require less floor space because the vertical orientation of the process chamber results in a relatively small footprint.
Both horizontal-type and vertical-type furnaces are designed to heat semiconductor wafers to desired temperatures to promote either diffusion of implanted dopants to a desired depth while maintaining line widths smaller than one micron, as known, or to perform other conventional processing techniques, such as the application of an oxide layer to the wafer or deposition of a chemical vapor layer to the wafer in a CVD process. Uniform heating of the wafer being processed, as well as uniform gas flow across the surface of the wafer, are critical in these processes.
Conventional vertical-type thermal processing furnaces, utilizing process chambers such as tube or bell jar furnaces, are designed to support the process tube within the furnace in a vertical position. Such vertical-type furnaces also typically employ either an elevator driven pedestal upon which a single wafer resides, or a wafer boat assembly for holding a plurality of wafers, along with appropriate translation mechanisms for moving the wafer(s) in and out of the process tube. Gas injection means are provided for furnaces in which oxide-forming or CVD processes are to be performed. As the critical dimensions for silicon integrated circuits are continuously scaled downward into the sub-micron regime, requirements for both wafer temperature uniformity and gas flow uniformity, as well as wafer-to-wafer process repeatability, become more stringent.
Prior art techniques and mechanisms for providing uniform gas flows in the processing chamber include, for a batch (wafer boat) environment, perforated gas tubes running the vertical length of the tube. Such a system is shown in U.S. Pat. No. 5,029,554 to Miyashita et al. In a single wafer environment, known mechanisms for controlling gas distribution flows across the wafer surface include that shown in U.S. Pat. No. 5,062,386 to Christensen, wherein a central passageway directs a portion of the gas flow toward the top of the bell jar, and imparts a radial component to another portion of the gas flow, to obtain a desired distribution of gas flow in the process chamber.
Alternatively, a quartz injector tube vertically positioned along an inside wall of the processing chamber may be provided. The injector tube may be either perforated along its length, or provide an outlet near the top thereof for gas injection into the processing chamber. The gas flow patterns provided by such injector tubes, however, are not axisymmetric with respect to the longitudinal axis of the processing chamber, providing instead asymmetic gas flows with inherent eddy currents.
Still further, a showerhead-type gas distribution device, such as a baffle plate, may be employed to evenly disperse gas over the surface of a wafer, as shown in U.S. Pat. Nos. 5,653,806 or 5,976,261. In the case of such a showerhead-type gas baffle plate, deformation or “sag” of the structure of the baffle plate, caused by high temperature processing, may result in uneven gas distribution across the surface of the wafer. Such deformation is particularly problematic is the baffle plate is constructed from quartz. Accordingly, prior art designs such as that shown in U.S. Pat. Nos. 5,653,806 or 5,976,216 incorporate a temperature controlling mechanism adjacent to or integral with the shower head baffle plate. Such added components add both cost and complexity to the furnace design.
Accordingly, it is an object of the present invention to provide a simplified gas distribution mechanism that can withstand high temperature processes in a wafer processing system. It is a further object to provide such a mechanism in a vertical-type thermal processing furnace.
SUMMARY OF THE INVENTION
A thermal process chamber is provided for processing substrates contained therein, comprising (i) a main processing portion in which a substrate to be processed may be positioned, the processing portion defining a first area and providing an opening through which a substrate to be processed may be inserted into and removed from the first area of the process chamber; (ii) an upper portion, positioned above the main processing portion, defining a second area and providing a closed end for the process chamber; (iii) a gas injector for providing gas to the second area; and (iv) a gas distribution plate separating the first area from the second area. The gas distribution plate provides a plurality of passageways for permitting gas provided to the second area to pass into the first area. The gas distribution plate is formed integrally with the main processing portion and with the upper portion. In one embodiment, the entire thermal process chamber, including the main processing portion, the upper portion, the gas injector, and the gas distribution plate are comprised of silicon carbide (SiC).


REFERENCES:
patent: 5029554 (1991-07-01), Miyashita et al.
patent: 5062386 (1991-11-01), Christensen
patent: 5131842 (1992-07-01), Miyazaki et al.
patent: 5160545 (1992-11-01), Maloney et al.
patent: 5318633 (1994-06-01), Yamamoto et al.
patent: 5653806 (1997-08-01), Van Buskirk
patent: 5653808 (1997-08-01), MacLeish et al.
patent: 5928427 (1999-07-01), Hwang
patent: 5976261 (1999-11-01), Moslehi et al.
U.S. application No. 09/476,525, Ko et al., filed Jan. 3, 2000.

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