Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Logic design processing
Reexamination Certificate
2008-11-25
2011-11-08
Dinh, Paul (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Integrated circuit design processing
Logic design processing
C716S108000, C716S134000
Reexamination Certificate
active
08056030
ABSTRACT:
A behavioral synthesis system has a scheduling unit and a mode control unit. The scheduling unit performs scheduling of a behavioral level description with reference to a resource quantity data indicating resource constraint and a resource delay data indicating delay times of respective resources. A single process described in the behavioral level description is divided into a plurality of description blocks, and a scheduling mode among a plurality of scheduling modes is designated with respect to each of the plurality of description block. The mode control unit refers to a mode designation code that indicates the designated scheduling mode and controls such that the scheduling unit performs the scheduling with respect to each description block in accordance with the designated scheduling mode indicated by the mode designation code.
REFERENCES:
patent: RE40925 (2009-09-01), Ly et al.
patent: 2002/0053069 (2002-05-01), Ohnishi et al.
Knapp, D. et al., Behavioral Synthesis Methodology for HDL-Based Specification and Validation, 1995, Design Automation, 1995. DAC '95. 32nd Conference on, pp. 286-291.
“Behavioral Synthesis: Digital System Design Using the Synopsis Behavioral Compiler”, Jun. 1999, pp. 57-60, Prentice Hall.
Akashio Hiroshi
Noda Shinichi
Aisaka Bryce
Dinh Paul
NEC Corporation
NEC Information Systems, Ltd.
Sughrue & Mion, PLLC
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