Behavioral synthesis links to logic synthesis

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364578, 364488, 364489, 364490, 364491, G06F 1900

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060262192

ABSTRACT:
A method and an apparatus for coupling the results of behavioral synthesis with those of logic synthesis. It uses a timing verifier to precalculate the timing characteristics of a circuit for use by behavioral synthesis. Timing for control chaining is included in the precalculated timing characteristics. Once behavioral synthesis is complete, logic synthesis is informed of timing constraints introduced by behavioral synthesis.

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