BDC corrected adder

Details BDC corrected adder BDC corrected adder

1975-07-21

1977-01-04

Smith, Jerry

Registers

Transfer mechanism

Traveling pawl

G06F 750

Patent

active

040015670

ABSTRACT:
A BCD corrected serial adder includes an adder circuit and an asynchronous programmable logic array (PLA) connected to an output of the adder circuit. Whenever the sum of two bytes exceeds the decimal number 9 in the addition mode, the PLA simultaneously generates each bit of a byte which is equal to that sum plus the BCD equivalent of the decimal number 6. Whenever the sum of a minuend and the 2's compliment of the subtrahend is less than zero, the PLA simultaneously generates each bit of a byte which is equal to that sum plus the BCD equivalent of the decimal number 10. A circuit responsive to a carry supplied at an output of the PLA and to the most significant bit of the most significant digit of the subtrahend word generates a borrow which can be employed immediately by a main control circuit for making the necessary correction when the subtrahend word is larger than the minuend word.

REFERENCES:
patent: 2947479 (1960-08-01), Selmer
patent: 2989237 (1961-06-01), Duke
patent: 3089644 (1963-05-01), Wensley
patent: 3304418 (1967-02-01), Perotto et al.
patent: 3508037 (1970-04-01), Collins et al.
patent: 3694642 (1972-09-01), Grannis

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