BCD adder circuit

Details BCD adder circuit BCD adder circuit

1987-07-09

1989-02-14

Harkcom, Gary V.

Boots, shoes, and leggings

364771, 364787, G06F 750

Patent

active

048051314

ABSTRACT:
The binary coded decimal (BCD) adder circuit for adding two BCD encoded operands and for producing a BCD encoded sum includes a bank of parallel full adder circuits as a first stage which generate an intermediate sum vector and an intermediate carry vector from the sum of the operands and a precorrection factor. A second stage of the BCD adder circuit includes carry lookahead adder circuitry receiving as inputs the intermediate sum vector and the intermediate carry vector and producing a propagate vector and a final carry vector. The third stage of the BCD adder circuit conditionally modifies the propagate vector to form the BCD encoded sum according to bits of the intermediate carry vector and the final carry vector as inputs.

REFERENCES:
patent: 3935438 (1976-01-01), Grupe
patent: 4001570 (1977-01-01), Gooding
patent: 4172288 (1979-10-01), Anderson
patent: 4638300 (1987-01-01), Miller
patent: 4707799 (1987-11-01), Ishikawa
patent: 4718033 (1988-01-01), Miller
Agrawal, D. P., "Fast BCD/Binary Adder/Subtractor", Electronics Letters, vol. 10, #8, pp. 121-122, 4/18/74.
Cavanagh, Joseph J. F., Digital Computer Arithmetic, Design and Implementation, pp. 306-311 (McGraw-Hill Book Company 1984).

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