Battery voltage detection device

Electricity: battery or capacitor charging or discharging – Serially connected batteries or cells

Reexamination Certificate

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Details

C320S122000

Reexamination Certificate

active

06664761

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a battery voltage detection device suitably used for measuring a low impedance voltage which is not earthed; for example, the voltage of a battery mounted as a power supply for a motor on an electric vehicle, hybrid electric vehicle, or the like.
2. Description of the Related Art
In an electric vehicle, a hybrid electric vehicle, or the like, a motor is mounted as a power source. A battery is used as an electric power supply for the motor. Such a battery requires a high voltage and a high power output. Therefore, a battery pack including a plurality of serially-connected battery cells is used as the battery for driving the motor. Usually, rechargeable secondary batteries are used as the battery cells. Since a battery pack used in an electric vehicle requires a high voltage, the battery pack is mounted on a vehicle so as to be isolated from the chassis earth for safety reasons.
In the electric vehicle, a battery voltage detection device is provided for monitoring the occurrence of malfunctions in the battery pack. The battery voltage detection device detects the voltage of each battery block which includes a plurality of battery cells as one unit.
FIG. 3
shows an exemplary structure of such a battery voltage detection device.
In
FIG. 3
, a battery pack
11
includes a plurality of battery blocks
11
a.
A plurality of voltage detection terminals
12
are provided between the battery blocks
11
a.
Each voltage detection terminal
12
is connected to a respective one of a first plurality of FETs (field-effect transistors)
43
, which is a first switching element. Each of the first plurality of FETs
43
forms an SSR (solid-state relay). Some of the first plurality of FETs
43
, which are connected to the odd-numbered voltage detection terminals
12
in the battery pack
11
, are together connected to one terminal of a capacitor
46
and to a second FET
45
a
which is a second switching element. The remainder of the first plurality of FETs
43
, which are connected to the even-numbered voltage detection terminals
12
in the battery pack
11
, are together connected to the other terminal of the capacitor
46
and to a third FET
45
b
which is a third switching element.
The second FET
45
a
and the third FET
45
b
are connected to respective input terminals of a differential amplifier
20
. The differential amplifier
20
includes a first operational amplifier
21
. The second FET
45
a
is connected to a positive input terminal of the first operational amplifier
21
via a first resistor
22
a.
The third FET
45
b
is connected to a negative input terminal of the first operational amplifier
21
via a second resistor
22
b.
The positive input terminal of the first operational amplifier
21
receives, via a third resistor
22
c,
the output of a second operational amplifier
23
which generates a reference voltage. The output of the first operational amplifier
21
is fed back to the negative terminal of the first operational amplifier
21
via a fourth resistor
22
d.
The output of the first operational amplifier
21
is output to an A/D converter
30
as the output of the differential amplifier
20
.
A voltage dividing circuit
24
is a series circuit formed by resistors
24
a
and
24
b.
The potential of the connection point of the resistors
24
a
and
24
b
is input to the positive input terminal of the second operational amplifier
23
. The output of the second operational amplifier
23
is fed back to the negative input terminal of the second operational amplifier
23
.
In a battery voltage detection device having such a structure, the voltages of the battery blocks
11
a
in the battery pack
11
are detected in turn by the differential amplifier
20
.
In the first step of the voltage detection process, the second FET
45
a
and the third FET
45
b
connected to the differential amplifier
20
are turned off. Then, a first FET of the first plurality of FETs
43
, which is connected to the first voltage detection terminal
12
in the battery pack
11
, and a second FET of the first plurality of FETs
43
, which is connected to the second voltage detection terminal
12
in the battery pack
11
, are turned on. Thus, the first battery block
11
a
is connected to the capacitor
46
, and charges the capacitor
46
.
After the capacitor
46
has been charged, the pair of the FETs
43
are turned off, and then the second FET
45
a
and the third FET
45
b
are turned on. Thus, the voltage of the capacitor
46
is applied to the differential amplifier
20
.
In the differential amplifier
20
, a reference voltage of 2.5 V is applied from the second operational amplifier
23
to the positive input terminal of the first operational amplifier
21
via the third resistor
22
c.
Therefore, the voltage of the capacitor
46
, which has been input to the differential amplifier
20
, is detected within a range up to 5 V from a reference of 2.5 V.
Similarly, while the second FET
45
a
and the third FET
45
b
are off, the first FETs
43
connected to the second voltage detection terminal
12
and the third voltage detection terminal
12
are turned on, so that the capacitor
46
is charged with the second battery block
11
a.
Then, the first FETs
43
are turned off, and the second FET
45
a,
and the third FET
45
b
are turned on. Thus, the voltage of the second battery block
11
a
in the battery pack
11
is detected.
In this case, the polarity of the voltage which has been input to the first operational amplifier
21
of the differential amplifier
20
is opposite to that of the first battery block
11
a.
Therefore, the first operational amplifier
21
detects the voltage of the second battery block
11
a
within a range down to 0 V from a reference of 2.5 V.
Subsequently, the voltages of the other battery blocks
11
a
are detected in turn in a similar manner.
Although the voltages having the opposite polarities are input in turn from the battery blocks
11
a
forming the battery pack
11
to the differential amplifier
20
, the voltages are detected without switching the polarity of the reference potential of the first operational amplifier
21
. The detected voltages of the battery blocks
11
a
are input to the A/D converter
30
. In the A/D converter
30
, input voltages are A/D converted, and then output to a computing unit, such as a CPU.
However, in such a battery voltage detection device, each of the first plurality of FETs
43
, which forms an SSR, has an inter-terminal capacitance. This inter-terminal capacitance may cause problems in the detection of the voltages of the battery blocks
11
a.
Specifically, in order to detect the voltage of one of the battery blocks
11
a,
a pair of first plurality of FETs
43
connected to voltage detection terminals
12
of this battery block
11
a
are turned on, then the capacitor
46
obtains a voltage value substantially equal to that of the connected battery block
11
a.
However, when each of the first plurality of FETs
43
is turned off, each of the first plurality of FETs
43
is charged with an electric charge of the capacitor
46
, because each of the first plurality of FETs
43
has inter-terminal capacitance. Therefore, the voltage value of the capacitor
46
may vary. As a result, the voltages of the battery blocks
11
a
may not be detected with high precision.
Furthermore, when the number of the battery blocks
11
a
in the battery pack
11
is an even number, the number of the first plurality of FETs
43
connected to respective terminals of the capacitor
46
are different. In the case of detecting a voltage of an even-numbered battery block
11
a,
the number of the first plurality of FETs
43
connected to the capacitor
46
is increased by one, in comparison to the number of the first plurality of FETs
43
in the case of detecting a voltage of an odd-numbered battery block
11
a.
Thus, there is a difference in the inter-terminal capacitances connected to the capacitor
46
between the case of detecting the voltage o

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