Electricity: battery or capacitor charging or discharging – Battery or cell discharging – With charging
Reexamination Certificate
2002-04-23
2004-09-28
Vu, Bao Q. (Department: 2838)
Electricity: battery or capacitor charging or discharging
Battery or cell discharging
With charging
C320S134000, C320S149000
Reexamination Certificate
active
06798171
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a battery monitoring circuit capable of monitoring a state of a secondary battery and to a battery device provided with the secondary battery, a current limiting means, a battery state monitoring circuit, and the like.
2. Description of the Related Art
As show in
FIG. 2
, a battery state monitoring circuit
22
A is normally provided with battery voltage monitor terminals
5
to
9
or monitoring a plurality of batteries
1
to
4
, a COP terminal
10
that serves as a charge control transistor gate connection terminal for controlling the charging of the batteries
1
to
4
, a DOP terminal
11
that serves as a connection terminal to a discharge control transistor gate for controlling discharge of the batteries
1
to
4
, a VMP terminal
12
that serves as an over-current monitor terminal for monitoring an over-current state of the batteries
1
to
4
, and a CTL terminal
13
that serves as a microcomputer control terminal.
In a the battery device, of
FIG. 2
, the secondary batteries
1
to
4
, a charge control transistor
14
, a discharge control transistor
16
, and a microcomputer
21
are connected with a the battery state monitoring circuit
22
A and external terminals EB+ and EB−, respectively.
Either one or both of an external load
19
(for example, a CPU of a notebook personal computer etc.) that is operated by the supply of the electric power of the secondary batteries
1
to
4
and a charger
20
for charging the secondary batteries
1
to
4
is (are) connected between the external terminals EB+ and EB− of a battery device
23
A.
When an over-current detection circuit
15
detects that the voltage of the VMP terminal
12
has been lowered by a desired voltage from a VDD, it causes the DOP terminal
11
to output a discharge inhibiting signal “H”, to thereby make the FET
16
enter in a state of OFF. This is referred to as a discharge inhibiting state due to an over-current.
Also, during a charge/discharge inhibiting state due to an over-current state, battery state monitoring circuit
22
A (specifically, the over-current detection circuit
15
in
FIG. 2
) causes a pull-Up circuit
18
provided inside thereof be turned on ON and pulls up the VMP terminal
12
to the battery voltage monitor terminal
5
through a given impedance. Accordingly, the impedance of the external load
19
that was the cause of the over-current becomes sufficiently larger than the impedance of the pull-up circuit
18
(that is, there is no fear of occurrence of the over-current) an the potentials of the VMP terminal
12
and the external terminal EB+ nearly reach the value of VDD. The over-current detection circuit
15
detects that the voltage of the VMP terminal
12
has risen by a desired voltage from the VDD and then releases the over-current detection state. This is referred to as a return form the discharge inhibiting state due to the over-current.
On the other hand, when a discharge inhibiting signal (here, the discharge inhibiting signal is referred to as “H”) is input to the CTL terminal
13
from a microcomputer
21
due to a cause other than the over-current state, the batter state monitoring circuit
22
A causes the DOP terminal
11
to output “H”, which causes the FET
16
to turn OFF. This is referred to as to a discharge inhibiting state due to an instruction from a microcomputer.
The discharge inhibiting state due to an instruction from a microcomputer is released by a release signal from the microcomputer.
However in the conventional battery state monitoring circuit
22
A and the battery device
23
A, when the impedance of the external load
19
is large, there is a problem in that an oscillation of the external terminal EB+ occurs in a cycle described in steps 2. to 5. below during the discharge inhibiting state due to an instruction from a microcomputer. A example of the oscillating waveform is shown in FIG.
5
. The oscillation has no influence on the charge/discharge control of the battery device
23
A itself. However, there is a problem in that it may adversely affect the peripheral equipment as a noise source.
1. When the discharge inhibiting state by the microcomputer is entered, the FET
16
is turned OFF and the supply of power to the external terminal EB+ is stopped.
2. The external terminal EB+ is pulled down by the external load
19
so that its potential is lowered.
3. In this case, the potential of the VMP terminal
12
is also reduced together with that of the external terminal EB+, so that the batter state monitoring circuit
22
A recognizes the discharge inhibiting state due to the over-current.
4. As a result the pull-up circuit
18
is turned ON. In this case, when the impedance of the external load
19
is sufficiently larger than the impedance of the pull-up circuit
18
, the VMP terminal
12
and the external terminal EB+ are pulled up so that their potentials approach the VDD potential
5. Accordingly, the battery state monitoring circuit
22
A recognizes that he discharge inhibiting state due to the over-current is released, to thereby cause the pull-up circuit
18
to be turned OFF again.
6. The state returns to one described in step 2.
SUMMARY OF THE INVENTION
The present invention has been devised to solve the above-described problem. According to the construction of a battery state monitoring circuit and a battery device of the present invention, even when discharge is in response to an instruction from a microcomputer, an external terminal EB+ does not oscillate so that the occurrence of noise is prevented.
That is, in the case where a discharge inhibiting signal is input to the battery state monitoring circuit from an external source, the impedance of an over-current monitor terminal is kept constant.
REFERENCES:
patent: 5493197 (1996-02-01), Eguchi et al.
patent: 5525890 (1996-06-01), Iwatsu et al.
patent: 5530336 (1996-06-01), Eguchi et al.
patent: 5808446 (1998-09-01), Eguchi
patent: 5847544 (1998-12-01), Eguchi
patent: 5959593 (1999-09-01), Hoshi
patent: 6064182 (2000-05-01), Eguchi
patent: 6495989 (2002-12-01), Eguchi
Adams & Wilks
Seiko Instruments Inc.
Vu Bao Q.
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