Telecommunications – Transmitter and receiver at same station – Radiotelephone equipment detail
Reexamination Certificate
1998-10-23
2001-06-05
Urban, Edward F. (Department: 2683)
Telecommunications
Transmitter and receiver at same station
Radiotelephone equipment detail
C455S343200, C455S039000, C455S256000
Reexamination Certificate
active
06243597
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a battery-operated communications device comprising a radio frequency part, a baseband processing arrangement, and a timing control arrangement.
2. Description of the Related Art
A battery-operated communications device of the above kind is known from the article “A Multiple Clocking Scheme for Low Power RTL Design”, C. Papachristou et al., pp. 27-32, Proceedings of the 1995 Int. Symposium on Low Power Design, Dana Point, 23-26 April 1995. In said article it is described how CMOS core circuitry of a battery-operated device, such as a cellular phone, is re-designed to achieve power reduction in an active mode. In such devices power reduction is important so as to increase stand-by and talk times. For ecological reasons, use of batteries should be minimised. For ergonomical reasons, the weight and size of the communications device should be as low as possible. A non-overlapping multiple clocking scheme is described for clocking non-disjunct partitions. The working frequency of each partition module is f
, f denoting frequency and n being an integer. Such an approach requires a careful selection of partitions in the design phase. Besides, the clock structure is complicated. For disjunct clock circuitry an increased chip area is needed so that costs of IC (Integrated Circuit) manufacturing are increased.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a battery-operated communications device in which power reduction is achieved in a simple way, virtually without an increase of chip-area.
To this end the battery-operated communications device of the above kind is characterised in that the communications device comprises a continuously running reference clock oscillator which is coupled to the timing control arrangement, the communications device being arranged to operate in an active mode and a reduced power stand-by mode, the timing control arrangement being partitioned into a first logic block comprising synchronisation means for maintaining synchronisation during the reduced power stand-by mode, and comprising a clock frequency reduction means for generating a derived clock signal having a frequency lower than the clock frequency of the reference clock oscillator, which derived clock signal controls the first logic block during the reduced power stand-by mode. Herewith, only the clock control logic circuitry has to be re-designed, hardly requiring an increase of chip area as compared to a communications device without reduced power during stand-by mode. Because the reference clock oscillator is running at its nominal frequency both during the active mode and the stand-by mode, long start-up times are avoided. Herewith, management of mode switching and delay times is made simpler. The core design of the communications device is hardly modified. Because there is no real clock gating, no practical problems as regards clock skew occur.
The invention is based upon the insight that during stand-by mode power consumption can be reduced for circuitry which has to remain active during stand-by mode but with a reduced functionality so that operating speed can be reduced, while the reference clock oscillator runs with the same speed as during the active mode.
Embodiments are claimed in the dependent claims. Although a divider can be used as simple circuitry for reducing the clock frequency, other means such as a clock pulse delete arrangement can be used. If the logic to be controlled is edge sensitive logic, the duty cycle of the clock is not critical. If the logic is level sensitive, preferably the duty cycle of the clock signal is around 50%. In a simple embodiment, the first logic block can both generate a clock selection signal to control a multiplexer multiplexing the clock signal of the reference clock oscillator and the reduced clock signal and a clock buffer of circuitry such as a second logic block which can be switched off completely during the stand-by mode. Because of the simple structure of power reduction during the stand-by mode, independently other power consumption saving means can be applied such as reducing the power supply voltage, logic circuit minimalisation, optimum wiring layout, break-before-make clock buffer circuitry and so on.
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patent: 5805990 (1998-09-01), Ohki
patent: 5815821 (1998-09-01), Pettersson
patent: 5949812 (1999-09-01), Turney et al.
patent: 5953646 (1999-09-01), Hirasawa
patent: 2297854A (1996-08-01), None
patent: 2297883A (1996-08-01), None
By C. Papachristou et al. “A Multiple Clocking Scheme for Low Power RTL Design”, pp. 27-32, Proceedings of the 1995 Int. By Symposium on Low Power Design, Dana Point, pp. 23-26, Apr. 1995.
By H.W. Tuttlebee, “Cordless Telecommunications in Wurope”, Springer Verlag, 1990 Appendix 3, pp. 273-278.
Jackson Blane J.
U.S. Philips Corporation
Urban Edward F.
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