Electricity: power supply or regulation systems – Output level responsive – Using a three or more terminal semiconductive device as the...
Reexamination Certificate
2000-04-27
2002-02-26
Riley, Shawn (Department: 2838)
Electricity: power supply or regulation systems
Output level responsive
Using a three or more terminal semiconductive device as the...
C323S316000, C320S140000, C320S164000
Reexamination Certificate
active
06351110
ABSTRACT:
TECHNICAL FIELD
The present invention refers to a DC-DC converter usable as a battery charger and to a method for charging a battery.
BACKGROUND OF THE INVENTION
For charging batteries, for example batteries of cell phones, the use of DC-DC converters operating as battery chargers and able to perform various charging algorithms for NiCd, NiMH and Lilon batteries is known.
FIG. 1
illustrates a known step-down DC-DC converter usable as a battery charger.
The DC-DC converter, indicated as a whole by the reference number
1
, comprises a switch
2
, for example formed of a MOS transistor, the opening and closing whereof is controlled by a driving stage
4
, and presenting a first terminal connected to a supply line
6
biased at the voltage VCC and a second terminal connected, via a diode
8
, to ground; an inductor
10
and a sense resistor
12
series-connected between the second terminal of the switch
2
and a node
14
, which is in turn connected, via a diode
16
, to a positive pole of the battery
18
to be charged, which presents its negative pole connected to ground; a capacitor
20
connected between the node
14
and ground; and a voltage divider
22
, formed of two resistors
24
,
26
, connected in parallel to the battery
18
, and presenting an intermediate node
28
on which it supplies a voltage VFB proportional, through the division ratio, to the voltage VBAT present between the poles of the battery
18
.
The DC-DC converter
1
further comprises a differential voltage error amplifier
30
presenting an inverting terminal connected to the intermediate node
28
of the voltage divider
22
and receiving from the latter the voltage VFB, a non-inverting terminal receiving a reference voltage VREF, and an output terminal connected to an output node
32
; a differential current error amplifier
34
presenting an inverting terminal and a non-inverting terminal connected across the sense resistor
12
, and an output terminal connected to a node
36
of an output stage
38
of the voltage error amplifier
30
, which is thus shared between the voltage error amplifier
30
and the current error amplifier
34
; and an offset voltage generator
40
supplying an offset voltage VOFFS and interposed between the inverting terminal of the current error amplifier
34
and a terminal of the sense resistor
12
.
The voltage error amplifier
30
and the current error amplifier
34
arc biased through respective current generators
44
,
46
, supplying, respectively, a bias current IV and a bias current IP which are both of constant value.
The function of the offset voltage generator
40
is that of programming the charging current IBAT of the battery
18
. In fact, when the current error amplifier
34
is balanced, i.e., when the voltage between the inverting terminal and the non-inverting terminal is substantially zero, in the sense resistor
12
there flows a current which determines across it a voltage drop equal, and with opposite sign, to the offset voltage VOFFS, and this current defines the battery charging current IBAT. For example, in order to program a 1-A battery charging current using a 0.1-&OHgr; sense resistor, it is sufficient to generate a 100-mV offset voltage.
Finally, the DC-DC converter
1
comprises a zero-pole compensation network
48
including a resistor
50
and a capacitor
52
series-connected between the output node
32
and ground; and a differential comparator
54
known as PWM (Pulse Width Modulator) comparator, presenting an inverting terminal receiving a comparison voltage VC which has a sawtooth waveform, a non-inverting terminal connected to the output node
32
, and an output terminal connected to the input of the driving stage
4
of the switch
2
, basically operating as pulse width modulator and supplying at an output a voltage having a square waveform, and the duty cycle whereof is a function of the voltage present on the node
32
.
The output stage
38
of the voltage error amplifier
30
comprises a current mirror
60
including a first and a second NMOS transistor M
11
, M
12
having gate terminals connected together and to the drain terminal of the transistor M
11
, source terminals connected to ground, and drain terminals connected to respective loads, each of which consists of a PMOS transistor M
9
, M
10
, connected in turn to a supply line
80
set at the voltage VREG. In addition, the drain terminal of the transistor M
11
defines the node
36
to which the output terminal of the current error amplifier
34
is connected.
The operation of the DC-DC converter
1
is as follows. During the battery charging phase, the current error amplifier
34
prevails over the voltage error amplifier, and the DC-DC converter
1
operates in a current regulation condition, behaving as a constant current generator and regulating the voltage present across the sense resistor
12
so that this will assume a value equal to that of the offset voltage VOFFS supplied by the offset voltage generator
40
.
In particular, during the current regulation phase, the current error amplifier
34
supplies at an output the current IOUT necessary for maintaining the output stage
38
in equilibrium for the entire duration of the battery charging phase, and controls, via the comparator
54
, the duty cycle of the signal supplied by the comparator
54
itself so as to render the voltages present on its own inverting and non-inverting terminals equal.
The current error amplifier
34
performs a negative feedback. In fact, a possible variation in the battery charging current IBAT results in an unbalancing of the current error amplifier
34
, with consequent variation in the voltage of the output node
32
, and hence of the duty cycle of the output signal of the comparator
54
, which acts to restore the programmed value of the battery charging current IBAT.
During the current regulation phase, the battery
18
is thus charged with a constant current according to the value programmed via the offset voltage generator
40
, and the battery voltage VBAT increases progressively towards the full charge value VFIN up to which the voltage of the battery
18
is to be brought.
The current error amplifier
34
prevails over the voltage error amplifier
30
as long as the voltage error amplifier
30
is unbalanced, i.e., as long as the voltage VFB is lower than the reference voltage VREF, and hence the differential input voltage &Dgr;V=VREF−VFB present between the input terminals of the voltage error amplifier
30
is positive.
When the battery voltage VBAT approaches the full charge value VFIN, the differential input voltage &Dgr;V=VREF−VFB present between the input terminals of the voltage error amplifier
30
approaches zero, the current error amplifier
34
unbalances, whilst the voltage error amplifier
30
is in equilibrium and thus prevails over the current error amplifier
34
, so imposing a decrease in the battery charging current IBAT; the DC-DC converter
1
therefore enters the voltage regulation phase in which the voltage error amplifier
30
controls the battery voltage VBAT.
FIG. 2
shows a more detailed circuit diagram of the current error amplifier
34
and of the voltage error amplifier
30
, in which parts that are identical or equivalent to those of FIG. I are identified by the same reference numbers or letters.
According to what is illustrated in
FIG. 2
, the current error amplifier
34
presents a differential input stage
70
with PNP bipolar transistors in Darlington configuration so as to be compatible to ground.
In detail, the differential input stage
70
comprises a pair of PNP bipolar transistors Q
1
, Q
2
connected in differential configuration, which present source terminals connected together and to the current generator
46
supplying the bias current IP, the current generator
46
being in turn connected to the supply line
6
, collector terminals connected to respective loads, and base terminals connected to the emitter terminals of respective PNP bipolar transistors Q
3
, Q
4
defining, together with the transistors Q
1
Pappalardo Salvatore
Pulvirenti Francesco
Jorgenson Lisa K.
Riley Shawn
Seed IP Law Group PLLC
STMicroelectronics S.r.l.
Tarleton E. Russell
LandOfFree
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