Batcher-banyan network

Multiplex communications – Wide area network – Packet switching

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H04Q 1104

Patent

active

049107305

ABSTRACT:
A Batcher-banyan network which may be implemented using only two different IC chip designs is disclosed. The chips comprising the Batcher banyan network are arranged in adjacent horizontal and vertical stacks to minimize the lengths of electrical conductors connecting the chips.

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"Sorting Networks and Their Applications", K. E. Batcher, Proceedings of 1968 Spring Joint Computer Conference, pp. 307-314, 1968.
"Principles of CMOS VLSI Design," Addison-Wesley Publishing Company, 1985, Self-Routing Switching Network, S. C. Knauer, et al., Chapter 9 Systems Case Studies, pp. 424-447.
"Restructured DS3 Format for Synchronous Transmission (SYNTRAN)," R. Ballart, et al., Proc. Globecom '84, pp. 1036-1042, Nov. 1984.

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