Batch process for forming metal plugs in a dielectric layer of a

Details Batch process for forming metal plugs in a dielectric layer of a Batch process for forming metal plugs in a dielectric layer of a

1997-02-20

1999-03-09

Talbot, Brian K.

Coating processes

Electrical product produced

Integrated circuit, printed circuit, or circuit board

427350, 4271261, 438908, B05D 512

Patent

active

058797394

ABSTRACT:
A batch process for the high-pressure forming of metal plugs in the dielectric layers of semiconductor wafers. After holes are etched in the dielectric layer of each wafer, and a layer of a metal such as aluminum deposited over the dielectric, both the etching and the deposition being done in vacuum chamber cluster machines, the wafers are removed from the cluster machines and placed together in a high pressure chamber where they are subjected to high isostatic pressure that forces the metal into the holes.

REFERENCES:
patent: 4951601 (1990-08-01), Maydan et al.
patent: 5019234 (1991-05-01), Harper
Shterenfeld-Lavie et al, "A 3-Level 0.35.mu.m interconnection process using an innovative, high pressure aluminium plug technology", Twelfth International VLSI Multilevel Interconnection Conference, Jun., 1995, Session II, Paper C.

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