Batch erasable single chip nonvolatile memory device and erasing

Details Batch erasable single chip nonvolatile memory device and erasing Batch erasable single chip nonvolatile memory device and erasing

1997-07-31

1999-04-27

Fears, Terrell W.

Static information storage and retrieval

Floating gate

Particular biasing

36518528, 365218, G11C 1300

Patent

active

058986219

ABSTRACT:
A batch erasable single chip nonvolatile memory device and a method therefor of using the same provided with memory cells which are adapted to execute an erase operation by ejecting an electric charge, accumulated at floating gates by a program operation (including a pre-write operation) carries out, in sequence a first operation for reading memory cells of an erase unit and carrying out a pre-write operation on those nonvolatile memory cells at the floating gates of which electric charge is not stored, a second operation for carrying out a batch erase operation at a high speed for the nonvolatile memory cells of said erase unit with a relatively large energy under a relatively large erase reference voltage, a third operation for carrying out a read operation of said all erased nonvolatile memory cells and a write operation on those nonvolatile memory cells which are adapted to have a relatively low threshold voltage, and a fourth operation for carrying out a batch erase operation at a low speed for the nonvolatile memory cells of said erase unit with a relatively small energy under a relatively small erase reference voltages, or is provided with an automatic erasing circuit for executing these operations.

REFERENCES:
patent: 4903236 (1990-02-01), Nakayama et al.
patent: 5181188 (1993-01-01), Yamauchi et al.
patent: 5598368 (1997-01-01), Takahashi

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