Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons
Patent
1990-05-15
1991-10-08
Miller, Stanley D.
Electrical transmission or interconnection systems
Nonlinear reactor systems
Parametrons
307570, 307469, 364716, 357 43, 357 45, H03K 1901, H03K 19003, H03K 19082, H03K 19094
Patent
active
050557165
ABSTRACT:
An improved cell for use in a mask programmable gate array is disclosed herein. The preferred cell comprises two compute sections, each comprising two pairs of medium size P and N-channel transistors, two small N-channel transistors, and a single small P-channel transistor. Each cell also comprises a high efficiency drive section containing a single bipolar pull-up transistor, a large N-channel pull-down transistor, and a small P-channel transistor. By using this cell, an extremely high compute capability per die area is achieved.
REFERENCES:
patent: 4069494 (1978-01-01), Grundy
patent: 4161662 (1979-07-01), Malcolm et al.
patent: 4649294 (1987-03-01), McLaughlin
patent: 4701642 (1987-10-01), Pricer
patent: 4791320 (1988-12-01), Kawata et al.
patent: 4804868 (1989-02-01), Masuda et al.
"Characterization of Speed and Stability of BiNMOS Gates with a Bipolar and PMOSFET Merge Structure," by Momose et al., published in IEDM, 1990.
Wong et al., IEEE, 1988 CICC, "A High Density BiCMOS Direct Drive Array".
Suehiro et al., IEEE, 1988, "A 120K-Gate Usable CMOS Sea of Gates Packing 1.3M Transistors", Custom Integrated Circuits Conference.
Y. Enomoto, "A 200K Gate 0.8 um Mixed CMOS/BiCMOS Sea-of-Gates," ISSCC 90.
J. Gallia, "High Performance BiCMOS 100K-Gate Array," paper.
H. Veendrick, "An Efficient and Flexible Architecture for High-Density Gate Arrays," ISSCC 90.
A. Watanabe, "Future BiCMOS Technology for Scaled Supply Voltage", 1989 IEEE IEDM.
T. Hanibuchi, "A Bipolar-PMOS Merged Basic Cell for 0.8 .mu.m BiCMOS Sea-of-Gates", IEEE 1990 CICC.
K. Kumagai, "A 150K Gate 250ps BiCMOS SOG with an Emitter-Followered CMOS (ECMOS) Cell", IEEE 1990 CICC.
W. Chin, "Push-Pull Driver Using Bipolar and Complementary Metal-Oxide Semiconductor Devices", IBM Technical Disclosure Bulletin, vol. 16, No. 11, Apr. 1974.
W. Pricer, "Combination CMOS/Bipolar Driver for high Capacitance", IBM Technical Disclosure Bulletin, vol. 27, No. 4A, Sep. 1984.
T. Sunaga, "Merged Bipolar-CMOS Device", IBM Technical Disclosure Bulletin, vol. 28, No. 8, Jan. 1986.
H. Fukuda et al., "A BiCMOS Channelless Masterslice with On-Chip Voltage Converter", International Solid State Circuits Conference (ISSCC) 1989, published Feb. 16, 1989.
A. Alvarez, pp. 237 and 238 of the book entitled "BiCMOS Technology and Applications".
K. Sawada, "A 72K CMOS Channelless Gate Array with Embedded 1M bit Dynamic RAM", IEEE 1988 CICC.
A. Hui, "A Sub Half-ns 237K Gate CMOS Compacted Array", IEEE 1988 CICC.
H. Hara, "A 350ps 50K 0.8 .mu.m BiCMOS Gate Array with Shared Bipolar Cell Structure", IEEE 1989 CICC, May 15, 1989.
F. Murabayashi, "A 0.5 .mu.m BiCMOS Channelless Gate Array", IEEE 1989 CICC, May 15, 1989.
J. Gallia, "A 100K Gate Sub-Micron BiCMOS Gate Array", IEEE 1989 CICC, published May 15, 1989.
A. Denda, "A 270 ps/24.000 Gate BiCMOS Gate Array", IEEE 1989 CICC, published May 15, 1989.
A. El Gamal (Applicant), "BiNMOS: A Basic Cell for BiCMOS Sea-of-Gates".
T. Hayashi, "SDC Cell-A Novel CMOS/BiCMOS Design Methodology for Mainframe Arithmetic Module Generation", IEEE 1989 CICC, May 15, 1989.
"BiCMOS Circuit Technology for a High-Speed SRAM," by Douseki et al., IEEE Journal of Solid-State Circuits, vol. 23, No. 1, Feb. 1988.
Bertelson David R.
Miller Stanley D.
SiArc
LandOfFree
Basic cell for BiCMOS gate array does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Basic cell for BiCMOS gate array, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Basic cell for BiCMOS gate array will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-258799