Basic cell for a gate array arrangement in CMOS Technology

Details Basic cell for a gate array arrangement in CMOS Technology Basic cell for a gate array arrangement in CMOS Technology

1988-02-04

1989-11-28

LaRoche, Eugene R.

357 45, H01L 2702, H01L 2710, H01L 2715

Patent

active

048841153

ABSTRACT:
A gate array arrangement provides basic cells in a core region, with logic functions or storage functions being realized by wiring these basic cells. The basic cells are composed of six or seven transistors in CMOS technology, with three p-channel transistors (TR1) in a a first region (BE1) and three n-channel transistors (TR2) in a second region (BE2), with the terminals (GTA) of the gate electrodes (GT1, GT2) of the transistors being arranged between these two regions (BE1, BE2). A further transistor (TR3) that has a smaller channel width than the remaining transistors (TR1, TR2) is arranged outside of the region (BE2) for the n-channel transistors (TR2). The gate electrode (GT3) of the further transistor lies parallel to the electrodes (GT2) connected to the gates of the n-channel transistors (TR2) but is shorter. The terminal (GTB) of the gate electrode (GT3) of the further transistor (TR3) faces toward the line for the supply voltage (VSS). The terminals (GTA) of the gate electrodes of the n-channel and p-channel transistors lie next to one another and can thus be connected to one another by the shortest possible path, and adequate space is available over the regions (BE1, BE2) to conduct wiring lines above the cell.

REFERENCES:
patent: 4562453 (1985-12-01), Noguchi et al.
patent: 4668972 (1987-05-01), Sato et al.
patent: 4740827 (1988-04-01), Niitsu et al.
Nakaya et al. "High Speed MOS Gate Array" IEEE Transactions on Electron Devices vol. ED-27 No. 8 Aug. 1980.
Electronics & Communications in Japan, "Design of CMOS Masterslide Logic LSI", Vol. 66, Jan. 1983, pp. 111-119.
Hitachi Review, "Development of Hybrid Gate Array", Vo. 33, 1984, pp. 261-266.

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