Basic cell architecture for mask programmable gate array with 3

Details Basic cell architecture for mask programmable gate array with 3 Basic cell architecture for mask programmable gate array with 3

1991-06-18

1994-02-22

Hille, Rolf

Active solid-state devices (e.g., transistors, solid-state diode

Gate arrays

Having specific type of active device

257208, 257210, H01L 2702, H01L 2710

Patent

active

052890210

ABSTRACT:
A highly efficient CMOS cell structure for use in a metal mask programmable gate array, such as a sea-of-gates type gate array, is disclosed herein. In a basic cell, in accordance with one embodiment of the invention, three or more sizes of N-channel transistors and three or more sizes of P-channel transistors are used. The larger size transistors are incorporated in a drive section of a cell, while the smaller size transistors are incorporated in each compute section of a cell. The particular transistors in the compute and drive sections and the arrangements of the compute and drive sections provide a highly efficient use of silicon real estate while enabling the formation of a wide variety of macrocells to be formed.

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