Baseline wander compensation circuit and method

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Amplitude control

Reexamination Certificate

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Details

C327S062000

Reexamination Certificate

active

06211716

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to the field of data communication and more particularly to a circuit and method for compensating for baseline wander occurrences in data signals.
BACKGROUND OF THE INVENTION
In 100 Base TX applications of a Copper Distributed Data Interface (CDDI), a data signal is transmitted across a twisted-pair copper wire that is commonly known as CAT-5 cable. The data signal is then AC coupled through a primary side of a transformer and received by a receiver connected to the secondary side of the transformer. This method of AC coupling the data signals through the transformer may cause the average DC value of the signal to drift (i.e., wander) significantly over time, as shown in
FIG. 1
a
. The data signal
100
is a waveform of an ideal MLT-3 signal, while the data signal
105
is a waveform of an MLT-3 signal that has been affected by Baseline Wander.
Baseline Wander occurs due to the high pass characteristics of the transformer. The transformer will suppress the DC level if data signal remains in the same level for a long time. This can cause the data signals to “droop” over time, as illustrated in
FIG. 1
a
. This drooping behavior may accumulate over time and may cause a maximum offset of 750 mV, differentially.
In the process of receiving and recovering data, uncompensated Baseline Wander offset can cause serious signal distortions due to the limited linear range of the amplifiers along the data path and can cause high jitter. This makes data slicing difficult and results in received errors. Therefore, Baseline Wander correction is important in the recovery of transmitted data signals.
An overview of a typical offset cancellation circuit is now discussed to provide better understanding of conventional approaches.
FIG. 1
b
is a schematic block diagram of an offset cancellation circuit
120
, which includes a forward path block
121
with a gain of A
1
, feedback path block
122
with a feedback gain of A
2
, and a summing point
125
. Equation (1) expresses the differential output voltage Vo of circuit
120
and explains the offset cancellation function.
[(V
IN
+&Dgr;v)−(A
2
)(Vo)]A
1
=Vo  (1)
The term V
IN
is the input signal in circuit
120
while &Dgr;v is the offset voltage added to the input signal V
IN
. The equations (2) and (3) can then be subsequently derived from equation (1).
A
1
(V
IN
+&Dgr;v)=[1+(A
1
)(A
2
)]Vo  (2)
Vo=(V
IN
+&Dgr;v)A
1
/[1+(A
1
)(A
2
)]  (3)
For stability of the feedback system in
FIG. 1
b
, the feedback gain A
2
has a low pass characteristic such that it has a high gain (i.e., A
2
>>1) at low frequency operation and has a very small gain (i.e., A
2
<<1) at high frequency operation. For a low frequency gain, A
2
>>1, the term [1+(A
1
×A
2
)] represents the denominator in the equation (3) and, therefore, the denominator also has a large value. As a result, the effect of offset is minimized. However at high frequency, the denominator of equation (3) approaches a unity value and equation (3) can be approximated as equation (4).
Vo=(V
IN
+&Dgr;v)×A
1
  (4)
It is noted that in the case where equation (4) is satisfied, the offset voltage &Dgr;v can not be canceled. Since the baseline wander effect is not a constant DC effect but an AC phenomenon, it is not cancelable by use of the offset cancellation circuit
120
.
A conventional Baseline Wander compensation version of an offset cancellation circuit
120
is shown in the circuit
150
of
FIG. 1
c
. The circuit
150
includes a feed forward path block
121
with a gain of A
1
, the feedback path block
155
with a gain of A
2
and a summing point
125
. The feedback path block
155
compares the output signal Vo with a replicated ideal signal
130
, which has the same DC bias, DC gain and AC gain as an ideal output signal Vo
(ideal)
with no Baseline Wander offset. As the Baseline Wander event occurs at the input signal V
IN
and consequentially at the output signal Vo, the feedback stage
155
detects this offset by comparing the output voltage Vo with the replica
130
and outputs a feedback signal
140
to compensate for Baseline Wander. As a result of this compensation, the offset or baseline wander is minimized at the input of the feed forward path block
121
.
However in practice, there is a phase difference between the replica signal
130
and the output signal Vo, as shown in
FIG. 1
d
. Although the effects of a phase difference can be “smoothed” out by using the low pass filter in the feedback path
155
, the phase difference still causes some unwanted ripple in the output signal
140
. As a result, the data output Vo has excessive jitter (noise) due to the offset ripple into the summing point
125
and then amplified by
121
.
Another problem, which is more severe, is the variations and mismatches in either DC gain and AC gain of the output signal Vo and its ideal replica
130
as shown in
FIG. 1
e
. Even though there is no phase shift in this case, the gain mismatch causes a residue signal that translates into offset ripple (Vo-Replica signal
130
). Notice that Vo is the output of an analog signal and replica signal
130
is synthesized from a digital data. The two waveforms cannot be match perfectly in terms of overshoot and rise/fall time and it is very difficult for the forward block
121
to have a fix gain over process, temperature and supply voltage. This results in unwanted ripples and potential errors. These ripples are the results of phase delay and gain mismatch and are always present regardless of the effect of baseline wander. Consequently, the performance of this replica approach is very limited.
Therefore, there is a need for a baseline wander compensation approach that overcomes the unwanted ripples and errors in conventional baseline wander compensation systems.
SUMMARY OF THE INVENTION
The apparatus and method of the present invention operates to track and dynamically compensate for the Baseline Wander event. The apparatus includes a first peak detector for receiving a first signal from a forward path stage and capable of detecting a peak of the first signal, and a second peak detector for receiving a second signal from the forward path stage and capable of detecting a peak of the second signal. The apparatus also includes a differential amplifier coupled to the first peak detector and the second peak detector and capable of generating an offset control signal, and a compensation stage coupled to the differential amplifier and capable of compensating for offset in the received signal in response to the offset control signal.
In another aspect of the present invention, the apparatus may also include a pair of selective sample peak detectors that are capable of sampling a portion of the input signal. The sampled portion of the input signal is defined by a “smart window” (timing window) which is received by a sample and block circuit of the peak detector. By making uses of these peak detectors and the smart or timing windows, the present invention is able to detect correctly the peak levels of the positive and negative signals independently and compares these levels for any potential offset caused by a Baseline Wander event. The present invention then outputs a Baseline Wander control signal to compensate for Baseline Wander.
The method of Baseline Wander compensation in accordance with the present invention is able to compensate the offset in data signals independently of its AC and DC gain. Furthermore, the present invention provides a Baseline Wander compensation approach that is fully differential, thereby permitting a circuit in accordance with the present invention to have improved immunity to noise.


REFERENCES:
patent: 4575683 (1986-03-01), Roberts et al.
patent: 5267269 (1993-11-01), Shih et al.
patent: 5428307 (1995-06-01), Dendinger
patent: 5539779 (1996-07-01), Nagahori
patent: 5546027 (1996-08-01), Shinozaki et al.
paten

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