Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – Unwanted signal suppression
Reexamination Certificate
2003-01-13
2004-03-09
Cunningham, Terry D. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
Unwanted signal suppression
C327S307000, C327S337000
Reexamination Certificate
active
06703894
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to receiver circuits, and more particularly, to filter circuits within a receiver.
DESCRIPTION OF THE RELATED ART
In recent years, the use of direct conversion receivers has begun to replace the use of heterodyne receivers in various types of wireless devices. Direct conversion receivers eliminate the need for an intermediate frequency (IF) conversion before converting a signal to its baseband frequency. Instead, a direct conversion receiver converts a received radio frequency (RF) signal directly to its baseband frequency.
One problem with many radio receiver circuits, including direct conversion receivers, is the presence of a DC (direct current) offset that may be present in the information signal output by the receiver. If the DC offset is large enough, it may hinder or altogether prevent the recovery of information carried on the received RF signal. For example, in FM receivers, it is important that the zero-crossing of an information signal not be obscured by a DC offset in the information signal.
FIG. 1A
illustrates an information signal without any DC offset. In this particular example, the information signal is a series of sine waves, which represent a logic 1 or a logic 0. When the information contained in the signal transitions from a logic 1 to a logic 0, the phase of the sine wave may shift by 180 degrees. In order to detect this phase shift, it is important that the signal pass through the zero crossing shown in the drawing. In
FIG. 1B
, a similar information signal with a substantial DC offset is shown. In this particular example, the information signal does not pass through the zero crossing due to the DC offset. Thus, the information present in the signal may not be recovered.
Rejection of DC offsets in information signals may be performed by filters having a low-frequency zero (in the filter transfer function). The zero must be at a frequency low enough to prevent rejection of the desired information signal. Various methods may be employed to accomplish the rejection of any DC offset present. In some implementations, a DC offset may be stored when the receiver is not in use, and this DC offset may be subtracted from the information signal when the receiver is in use. Digital signal processing (DSP) techniques may also be employed. AC (alternating current) coupling methods, which use large decoupling capacitors in series with the baseband filters, may be used in some implementations. Each of these methods has certain disadvantages. Receiver circuits which store the DC offset and subtract it as an error signal may not be able to account for a dynamically shifting DC offset. DSP solutions may require significant processing capability, and may consume more power than is desirable, particularly for portable devices. AC coupled circuits may require large capacitors that may not be practically integrated, which then requires external components that increase component count and cost.
SUMMARY OF THE INVENTION
A filter circuit is disclosed. In one embodiment, the filter circuit includes a continuous time (CT) filter, a switched capacitor (SWC) filter, and an SWC integrator. The CT filter is coupled to receive an input signal from an external source (e.g., a down conversion mixer in a direct conversion receiver). The CT filter may be a low-pass filter. The SWC filter is coupled to receive an output signal from the CT filter, and provide an output information signal. In one embodiment, the output signal may be a continuous signal. The SWC filter may also be a low pass filter. An SWC integrated may be coupled in a feedback loop between the output of the SWC filter and the input of the CT filter. The SWC integrator may sample the output signal from the SWC filter and provide an output signal to the input of the CT filter. The output signal may be combined with the input signal to the CT filter. A D.C. (direct current) offset may be substantially removed from the information signal provided by the output of the SWC filter.
A method for rejecting a DC offset in a filter circuit includes providing an input signal, performing a continuous time filtering function, and providing an output signal. The method may then perform an SWC filtering function to provide an information signal as an output. The method may further include sampling the information signal, performing an SWC integrating function, and providing an output signal to the input of a CT filter. The output signal from the SWC filtering function may be combined with the input signal to the CT filtering function. A DC offset component may be substantially removed from the information signal responsive to combining the input signal and the continuous output signal.
REFERENCES:
patent: 6313685 (2001-11-01), Rabii
patent: 6317064 (2001-11-01), Ferrer et al.
patent: 6429733 (2002-08-01), Pagliolo et al.
patent: 2003/0098734 (2003-05-01), Herdey et al.
Stockstad Troy L.
Wortel Klaas
Cunningham Terry D.
Hood Jeffrey C.
Meyertons Hood Kivlin Kowert & Goetzel P.C.
Standard Microsystems Corporation
Tra Quan
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