Baseband digital offset correction

Details Baseband digital offset correction Baseband digital offset correction

2000-05-03

2001-11-06

JeanPierre, Peguy (Department: 2819)

Coded data generation or conversion

Converter compensation

C341S120000

Reexamination Certificate

active

06313769

ABSTRACT:

TECHNICAL FIELD
The present invention relates, in general, to wireless mobile communications and, more particularly, to calibrating a digital-to-analog converter (DAC) in a mobile telephone.
BACKGROUND OF THE INVENTION
In wireless mobile communications, a codec device is typically used to perform analog-to-digital conversion or digital-to-analog conversion of a baseband signal. Before transmitting the baseband signal, the signal must be amplified. Any DC-offset voltage present in the baseband signal is also amplified, causing signal distortion and saturation. As a result, the DC-offset voltage must be eliminated by determining its level and subtracting that level from the baseband signal.
Early generation cellular phones transmit short bursts of signals. DC-offset compensation is achievable by storing the DC-offset voltage across a capacitor. Since transmission is in short bursts, the DC-offset value is calculated and stored across the capacitor before each burst of data. Problems of capacitor leakage influencing the stored DC-offset may largely be ignored.
Next generation cellular phones, on the other hand, using standards, such as GSM Phase II+ and WCDMA, require the mobile phone to transmit in multiple time slots or in continuous mode. As such, the baseband signal must be transmitted free of any DC-offset for extended periods of time. Continuous operation precludes storing the DC-offset across a capacitor. The DC-offset stored across the capacitor leaks away during the extended period of operation.
It is desirable, therefore, to solve the problem associated with baseband signal offset correction. This invention addresses that problem.
SUMMARY OF THE INVENTION
To meet this and other needs, and in view of its purposes, the present invention provides a signal processing system including a main digital-to-analog converter (DAC) for receiving a digital baseband signal and converting the digital signal into an analog signal. Also included in the system is a connection circuit for receiving the analog signal, an output terminal, and an analog filter coupled between the connection circuit and the output terminal for filtering the analog signal. The system includes a calibration circuit coupled between the connection circuit and the output terminal for setting an offset voltage level. The calibration circuit includes (a) an approximation circuit coupled to the output terminal and operable during a calibration mode to determine the offset voltage level and store the offset voltage level as a digital offset signal, and (b) an offset DAC coupled between the connection circuit and the approximation circuit for converting the digital offset signal into the offset voltage level. The connection circuit, which is a node, subtracts the offset voltage level from the analog signal.
In one embodiment, the main DAC receives the digital baseband signal as n-parallel bits and the offset DAC receives the digital offset signal as less than or equal to n/2 parallel bits. The approximation circuit includes a comparator connected to the output terminal for receiving the filtered analog signal and providing an intermediate offset voltage level during the calibration mode. The approximation circuit (a) receives the intermediate offset voltage level, (b) converts the intermediate offset voltage level into digital bits including a most significant bit (MSB) value and a least significant bit (LSB) value, and (c) subtracts a ½ LSB value from the intermediate offset voltage level to form the digital offset signal.
It is to be understood that both the foregoing general description a the following detailed description are exemplary, but are not restrictive, of the invention.


REFERENCES:
patent: 4196420 (1980-04-01), Culmer et al.
patent: 5381148 (1995-01-01), Mueck et al.
Paschal Minogue, “A 3V GSM Codec”,IEEE Journal of Solid State Circuits,vol. 30, No. 12, pp. 1411-1417 (Dec. 1995).
Frank Goodenough “12-Bit IC ADC's Guarantee ±1 LSB from −55° to +125° C.”Electronic Design,4 pages, (Sep. 3, 1992).

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