Base-to-substrate leakage cancellation

Details Base-to-substrate leakage cancellation Base-to-substrate leakage cancellation

2003-04-14

2004-08-17

Loke, Steven (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Bipolar transistor structure

C257S563000, C257S526000, C257S557000

Reexamination Certificate

active

06777781

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to vertical PNP transistors. More particularly, the present invention is related of extending the temperature based operating range of a vertical PNP transistor by minimizing the effects of flare-out and leakage currents.
BACKGROUND OF THE INVENTION
Bipolar junction transistors (BJTs) can be manufactured in a MOS process by using a vertical transistor structure. In one example, a vertical PNP transistor is fabricated by placing (e.g., diffusing) a p+ region inside an n-well, where the n-well is inside a p-substrate. Vertical PNP transistors are used, for example, in temperature sensor circuits, thermal voltage generators, and bandgap circuits.
The accuracy of temperature sensor that employs a vertical PNP transistor is poor for temperatures approaching 130 degrees Celsius and above. The reduced accuracy is largely due to higher order effects such as current that leaks from the base to collector junction area (i.e., between the n-well and the p+ material) in the vertical PNP transistors, as well as from other higher order effects. The higher order temperature inaccuracies can be reduced by increasing the current density of vertical PNP.


REFERENCES:
patent: 6369646 (2002-04-01), Kesler et al.
patent: 6650176 (2003-11-01), Lorenz

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