Boots – shoes – and leggings
Patent
1993-12-10
1995-07-18
Heckler, Thomas M.
Boots, shoes, and leggings
395650, 364DIG1, 3642712, 3642287, 3642283, G06F 1516, G06F 1580
Patent
active
054349958
ABSTRACT:
A barrier mechanism provides a low-latency method of synchronizing all or some of the processing elements (PEs) in a massively parallel processing system. The barrier mechanism is supported by several physical barrier synchronization circuits, each receiving an input from every PE in the processing system. Each PE has two associated barrier synchronization registers, in which each bit is used as an input to one of several logical barrier synchronization circuits. The hardware supports both a conventional barrier function and an alternative eureka function. Each bit in each of the barrier synchronization registers can be programmed to perform as either barrier or eureka function, and all bits of the registers and each barrier synchronization circuit functions independently. Partitioning among PEs is accomplished by a barrier mask and interrupt register which enables certain of the bits in the barrier synchronization registers to a defined group of PEs. Further partitioning is accomplished by providing bypass points in the physical barrier synchronization circuits to subdivide the physical barrier synchronization circuits into several types of PE barrier partitions of varying size and shape. The barrier mask and interrupt register and the bypass points are used in concert to accomplish flexible and scalable partitions corresponding to user-desired sizes and shapes with a latency several orders of magnitude faster than existing software implementations.
REFERENCES:
patent: 5083265 (1992-01-01), Valiant
patent: 5127092 (1992-06-01), Gupta et al.
Digital Equipment Corporation, digital.TM., "DECChip.TM. 21064-AA RISC Microprocessor Preliminary Data Sheet," .COPYRGT.Digital Equipment Corporation Apr. 29, 1992.
Harold S. Stone, "High-Performance Computer Architecture," pp. 336-338 and 398.
Digital Equipment Corporation, "EV3 and EV4 Specification DC227 and DC228," Revision/Update Information: Version 2.0 May 3, 1991.
James T. Kuehn and Burton J. Smith, "The Horizon Supercomputing System: Architecture and Software," pp. 28-34.
The Computer Society of the IEEE, "28th Annual Symposium on Foundations of Computer Science--(Formerly called the Annual Symposium on Switching and Automata Theory), sponsored by the Computer Society of the IEEE Technical Committee on Mathematical Foundations of Computing," Oct. 12-14, 1987, IEEE 87CH2471-1, pp. 185-194.
L. G. Valiant, Harvard University, Cambridge, Mass., "Optimally universal parallel computers," Phil. Trans. R. Sco. Lond. A. 326, pp. 373-376 (1988).
Geoffrey C. Fox and David W. Walker, California Institute of Technology, "A Portable Programming Environment for Multiprocessors."
Phillip B. Gibbons, Computer Science Division, University of California, "A More Practical PRAM Model," 1989 ACM 0-89791-323-X/89/0006/0158, pp. 158-168.
Clyde p. Kruskal, Larry Rudolph and Marc Snir, "Research Report--A Complexity Theory of Efficient Parallel Algorithms," RC 13572 (#60702) Mar. 4, 1988, Computer Science, 59 pages.
Fromm Eric C.
Oberlin Steven M.
Cray Research Inc.
Heckler Thomas M.
LandOfFree
Barrier synchronization for distributed memory massively paralle does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Barrier synchronization for distributed memory massively paralle, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Barrier synchronization for distributed memory massively paralle will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2421943