Adhesive bonding and miscellaneous chemical manufacture – Methods – Surface bonding and/or assembly therefor
Reexamination Certificate
2000-07-26
2001-09-04
Mayes, Curtis (Department: 1734)
Adhesive bonding and miscellaneous chemical manufacture
Methods
Surface bonding and/or assembly therefor
C156S089120, C156S089180, C029S851000, C264S620000, C174S257000
Reexamination Certificate
active
06284080
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to multi-layer ceramic packaging of hybrid micro-electronic devices, and methods of making and using same.
BACKGROUND OF THE INVENTION
Several methods currently exist for manufacturing ceramic networks or substrates employed in hybrid micro-electronic circuits. Current ceramic technologies include so-called High Temperature Co-Fired Ceramic Technology (HTCC), thick film technology, thin film technology and Low Temperature Co-Fired Ceramic technology (LTCC).
In standard HTCC processes, refractory metals such as tungsten or molybdenum are typically employed for conductor material. The typical HTCC product requires either electrolytic or electroless nickel and gold plating. Plating processes increase part costs. Electrolytic plating requires the design of an interconnection scheme of runners called plating bars for tying electrical nodes together and permitting the flow of electrical current required in an electrolytic process. Electrolytic plating also requires complicated, expensive equipment, and often results in increased electrical cross-talk and larger part size. Electroless plating of HTCC networks eliminates the requirement for plating bars, but may result in- gold thickness for wire bonding that are insufficient. Moreover, the electroless plating process commonly employed to manufacture HTCC networks is known to be somewhat unstable in respect of controlling plating thickness.
HTCC networks typically exhibit ceramic shrinkage variation that is excessive for automatic substrate processes or flip chip applications. HTCC does offer the advantage of a product that exhibits high flexural strength. Additionally, HTCC permits leads or seal rings to be brazed directly onto the substrate. This latter advantage is important in respect of some implantable medical devices, where hermetically sealed packages may be required.
Standard thick film processes employ multiple layers of conductor and dielectric material that are applied onto a pre-fired ceramic substrate. This method of manufacturing has been used for many years, and as a result printable dielectrics and metallizations are commercially available. Due to the high cost of precious metal conductor materials, the cost of a device increases as the number of interconnect layers increases. Consequently, as device complexity increases thick film processes become costly. Although thick film metallization systems may be employed at relatively low cost, such systems may suffer from problems such as silver migration. Thin film processes typically require vacuum deposition of a metallization surface layer onto a substrate followed by deposition of a polyimide or similar film thereon, and selective etching of the deposited film to form the desired circuitry pattern.
LTCC is a-variant of conventional thick and thin film processes, where dielectric screen printing is replaced with so-called “green sheets” of dielectric material having via holes filled with gold or silver and conductor layers printed on one or both sides of the sheets. The green sheets are laminated and die-cut into individual networks. The resulting sheets are fired in conventional furnaces at temperatures that typically range between about 800° C. and about 900° C. for periods of time that typically range between about 1 and about 3 hours.
An advantage of the LTCC process is the ability to use standard thick or thin film processing equipment when nickel or gold plating is not required. Unfortunately, the LTCC process commonly results in products having networks and substrates of low flexural strength. LTCC processes may be prohibitively expensive in applications where high reliability is required, such as in implantable medical device applications, because the gold pastes required for such applications are very expensive. Additionally, some LTCC processes have relatively large shrinkage variations associated with outside metallization.
The paper “Fast Turnaround Mutilayer Cofired Ceramic Motherboard Fabrication” by Hassler presented at the Second Electronic Packaging materials and Processes Conference in Minneapolis, Min. in October, 1985, discloses metallized multilayer cofired ceramic packages, where a substrate has external and internal electrically conductive patterns stacked in layers. High purity alumina ceramic separates and insulates the layers while conductive vias interconnect the-layers. Tungsten paste is used to create the conductive patterns and vias. Tungsten and alumina are cofired into a monolithic unit that is strong, hermetic, dimensionally stable and thermally conductive.
European Patent Application No. 93193541.4 to Hormadaly et al. entitled “Via Fill Components” discloses a thick film paste that is especially useful for via fill applications comprising finely divided particles of conductive metal which is not alloyable with silver selected from the group consisting of osmium, ruthenium, iridium, rhodium and mixtures and alloys thereof dispersed in a liquid organic medium. Optionally, a small amount of inorganic binder may be dispersed in the same medium.
European Patent Application No. 86309387.8 to Early entitled “Rhodium Capped Gold IC Metallization” discloses a two layer gold IC metallization process where a first gold metal layer is deposited atop a first barrier layer by electrodeposition, and a second metal layer or cap is deposited by electrodeposition atop the gold layer. After annealing, a dielectric layer is deposited, vias are formed in the dielectric layer, a second barrier layer is deposited, and a rhodium cap is deposited.
Page 104 of the March, 1984 issue of the publication “Research Disclosures” discloses the elimination of nickel/gold plated metallization by co-firing an alloy paste comprising palladium, platinum, rhodium, a binder and a vitreous frit that is screened in the via of the outer sheets of a multi-layer ceramic structure on top of molybdenum.
In addition to the foregoing Hormadaly et al. and Research Disclosure publications, other publications in the same general field include the U.S. Patents listed below in Table 1.
TABLE 1
Prior Art U.S. Patents
Patent No.
Title
4,316,942
Thick Film Copper Conductor Circuits
4,512,329
Copper Conductor Compositions
4,636,332
Thick Film Conductor Compositions
4,780,248
Thick Film Conductor Materials
4,819,056
Hybrid Thick Film Circuit Device
4,859,365
Conductive Paste Composition
4,910,643
Thick Film, Multi-Layer, Ceramic Interconnected Circuit
Board
4,961,999
Thermistor Composition
4,982,267
Integrated Semiconductor Package
5,122,302
Thick Film NTC Thermistor Compositions
5,162,062
Method for Making Multilayer Electronic Circuits
5,175,609
Structure and Method for Corrosion and Stress-
Resistant Interconnecting Metallurgy
5,294,567
Method for Forming Via Holes in Multilayer Circuits
5,303,457
Method for Packaging Microelectronic Frequency
Selection Components
5,318,820
HTCC/LTCC Use of Multiple Ceramic Tapes in High
Rate Production
5,324,370
Method of Manufacturing a Multi-Layer Ceramic Circuit
Board Containing Layers of Reduced Dielectric Constant
5,367,195
Structure and Method for a Superbarrier Between a
Noble and a Non-Noble Metal
5,391,917
Multiprocessor Module Packaging
5,496,619
Substrate Formed from Conductive Paste and
Insulating Paste
As those of ordinary skill in the art will appreciate readily upon reading the Summary of the Invention, Detailed Description of the Preferred Embodiments and Claims set forth below, many of the devices and methods disclosed in publications listed above may be modified advantageously by using the teachings of the present invention.
SUMMARY OF THE INVENTION
The present invention relates to multi-layer ceramic packaging of hybrid micro-electronic devices, including those for use in implantable medical devices.
The present invention permits size reduction and design simplification in such packaging by eliminating the need for electrolytic or electroless plating, and by eliminating or substantially eliminating the shrinkage variation typically associated with surface metallization techniques. Th
Haq Samuel F.
Malone Patrick F.
Varner Donald P.
Girma Wolde-Michael
Mayes Curtis
Medtronic Inc.
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