Barrier materials for metal interconnect in a semiconductor...

Details Barrier materials for metal interconnect in a semiconductor... Barrier materials for metal interconnect in a semiconductor...

2000-09-19

2002-02-05

Everhart, Caridad (Department: 2825)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C257S770000

Reexamination Certificate

active

06344691

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to semiconductors and more specifically to barrier materials used in semiconductor processing.
BACKGROUND ART
In the process of manufacturing integrated circuits, after the individual devices, such as the transistors, have been fabricated in the silicon substrate, they must be connected together to perform the desired circuit functions. This connection process is generally called “metalization”, and is performed using a number of different photolithographic and deposition techniques.
One metalization process, which is called the “damascene” technique, starts with the placement of a first channel dielectric layer, which is typically an oxide layer, over the semiconductor devices. A first damascene step photoresist is then placed over the oxide layer and is photolithographically processed to form the pattern of the first channels. An anisotropic oxide etch is then used to etch out the channel oxide layer to form the first channel openings. The damascene step photoresist is stripped and a barrier layer is deposited to coat the walls of the first channel opening to ensure good adhesion and to act as a barrier material to prevent diffusion of such conductive material into the oxide layer and the semiconductor devices (the combination of the adhesion and barrier material is collectively referred to as “barrier layer” herein). A seed layer is then deposited on the barrier layer to form a conductive material base, or “seed”, for subsequent deposition of conductive material. A conductive material is then deposited in the first channel openings and subjected to a chemical-mechanical polishing process which removes the first conductive material above the first channel oxide layer and damascenes the conductive material in the first channel openings to form the first channels.
For multiple layers of channels, another metalization process, which is called the “dual damascene” technique, is used in which the channels and vias are formed at the same time. In one example, the via formation step of the dual damascene technique starts with the deposition of a thin stop nitride over the first channels and the first channel oxide layer. Subsequently, a separating oxide layer is deposited on the stop nitride. This is followed by deposition of a thin via nitride. Then a via step photoresist is used in a photolithographic process to designate round via areas over the first channels.
A nitride etch is then used to etch out the round via areas in the via nitride. The via step photoresist is then removed, or stripped. A second channel dielectric layer, which is typically an oxide layer, is then deposited over the via nitride and the exposed oxide in the via area of the via nitride. A second damascene step photoresist is placed over the second channel oxide layer and is photolithographically processed to form the pattern of the second channels. An anisotropic oxide etch is then used to etch the second channel oxide layer to form the second channel openings and, during the same etching process to etch the via areas down to the thin stop nitride layer above the first channels to form the via openings. The damascene photoresist is then removed, and a nitride etch process removes the nitride above the first channels in the via areas. A barrier layer is then deposited to coat the via openings and the second channel openings. Next, a seed layer is deposited on the barrier layer. This is followed by a deposition of the conductive material in the second channel openings and the via openings to form the second channel and the via. A second chemical-mechanical polishing process leaves the two vertically separated, horizontally perpendicular channels connected by a cylindrical via.
The use of the damascene techniques eliminates metal etch and dielectric gap fill steps typically used in the metalization process. The elimination of metal etch steps is important as the semiconductor industry moves from aluminum to other metalization materials, such as copper, which are very difficult to etch.
One drawback of using copper is that copper diffuses rapidly through various materials. Unlike aluminum, copper also diffuses through dielectrics, such as oxide. When copper diffuses through dielectrics, it can cause damage to neighboring devices on the semiconductor substrate. To prevent diffusion, materials such as tantalum nitride (TaN), titanium nitride (TiN), and tungsten nitride (WN) are used as barrier materials for copper. A thin layer of adhesion material, such as titanium, is first formed on the dielectrics or vias to ensure good adhesion and good electrical contact of the subsequently deposited barrier layer to underlying doped region and/or conductive channels. Adhesion/barrier material stacks such as tantalum/tantalum nitride (Ta/TaN) and titanium/titanium nitride (Ti/TiN) have been found to be useful as adhesion/barrier material combination for copper interconnects. In the case of WN, it has been found that no adhesion layer is necessary because WN adheres well to dielectrics, such as oxide, and because it is an amorphous material making it a desirable barrier material for copper processes.
The “barrier effectiveness” of a barrier material layer with respect to a conductive material is its ability to prevent diffusion of the conductive material. The barrier effectiveness of a barrier material layer is determined in part by its thickness, including the thickness uniformity, and its quality, including the number and sizes of defects such as pinholes which form on deposition. To resist copper diffusion, it is found that a minimum barrier material thickness of 5 nm is required. However, to minimize the electrical resistance due to the barrier material layer, it is desirable to maintain a thin barrier material layer. Therefore, it is typical to keep the barrier material layer thickness close to about 5 nm. While it is generally easy to maintain a minimum thickness of 5 nm at the bottom of the channels or vias, it is difficult to do so at the sidewalls of the channels or the vias. Occasionally, there may be insufficient barrier material thickness at the sidewalls which would allow copper to diffuse through, causing damages to adjacent devices.
Another important factor to the barrier effectiveness of a barrier material layer is its chemical composition. In the case of a WN barrier layer, an increase in its nitrogen content increases its barrier effectiveness. A WN barrier layer with a higher nitrogen content is preferred because the increase in barrier effectiveness compensates for the thickness non-uniformity or presence of pinholes and makes the layer more robust in preventing diffusion of conductive material therethrough. However, an increase in the nitrogen content would also undesirably increase the electrical resistance of the barrier layer.
Another problem with using WN as a barrier material layer is that the crystallographic texture of the overlying copper layer is poor which means that it has poor resistance to electromigration of the copper which in turn leads to voids in the copper. Essentially, copper atoms in the channels and vias tend to migrate with the flow of current and form voids when the grains of the crystalline structure of the copper are not closely aligned.
Even further, WN precludes using a low temperature process and the high temperature made it difficult to integrate with many low k dielectric materials.
Generally, with higher resistivity materials such as WN, there have been two major problems. First they lead to high interface resistance between the high resistivity material and the layers below it, for example the lower level copper interconnect. Second, the thicker the material, the higher the resistance simply passing through the bulk of the high resistivity layer.
A solution, which would provide WN layers that result in an increase in its barrier effectiveness without an increase in its electrical resistance and an improvement in the texture of the overlying copper layers, has long been sought, but has eluded those skilled in the art.

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