Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – Insulating material
Reexamination Certificate
1999-05-03
2001-04-24
Lee, Eddie C. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
Insulating material
C257S700000, C257S701000, C257S702000, C257S703000
Reexamination Certificate
active
06222261
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to hybrid electronic and photoelectric devices manufactured by means of thin film and monolithic layering techniques.
2. Description of Prior Art
Most electronic devices are now made using thin layers of material on a supporting substrate such as silicon, gallium arsenide, mercury cadmium telluride, sapphire, plastic or one of various other similar types of materials. These devices are being combined with one another and other film structures in layers to form more exotic devices. Upon interfacing these layers and/or devices with each other special considerations have to be addressed such as electrical isolation, electrical conduction, thermal isolation, differential thermal expansion, and chemical compatibility.
As an example, large arrays of infrared photodetectors made with HgCdTe or pyroelectric materials are being combined with Charge-Coupled Devices (CCD's) made on silicon substrates. The photodiodes are very temperature sensitive and become extremely noisy unless maintained near the boiling point of liquid nitrogen. The CCD's work well at room temperatures and become an undesirable thermal load on the photodiodes unless adequate insulation is placed between them.
In applicant's patent application Ser. No. 07/823,749, filed Jan. 22, 1992 and issued Apr. 5, 1994 as U.S. Pat. No. 5,300,807, there is described a method of forming a thin layer of plastic which is sandwiched between hybrid devices, such as detector arrays and CCD's, during their assembly. It has been proposed that parts of these hybrid structures not be preassembled, but that the arrays be formed on the CCD structures, preferably on an aerogel insulating layer. It would also be advantageous not to preform the cross-linking electrodes on the CCD's; so that the same CCD's can be utilized in a variety of Time Delay Integration (TDI) readout scenarios with the same or different arrays. The surface of the aerogel, however, is too porous to form the semiconductor or metallization layers on, and the plastic preparation layer previously suggested cannot withstand the rigors of sputtering and other techniques used to form these layers.
SUMMARY OF THE INVENTION
To improve a hybrid microelectronic circuit chip, a dry process is used to join one or more nanostructured barrier layers to a first layer of the device, thereby forming a sturdy electrical and thermal barrier structure on which to form a succeeding layer. This barrier also may be added before and/or after the addition of a layer of material having an irregular and/or fragile surface, such as an aerogel. The term “nanostructured” as used in this application refers to a controlled layered or filamentary structure in the material which can limited to one nanometer, but broadly interpreted also includes such structures having minimum dimensions as large as a hundred nanometers.
One object of the invention, therefore, is to provide improved hybrid microelectronic devices which include nanostructured barrier layers that can be processed like a plastic, but are not damaged by wet chemical, sputtering and similar processing.
A further object of the invention is to provide an improved hybrid microelectronic device having at least one layer of delicate and/or porous material, such as an aerogel, coated with a nanostructured material as described above.
REFERENCES:
patent: 4882212 (1989-11-01), SinghDeo et al.
patent: 5057648 (1991-10-01), Blough et al.
patent: 5347426 (1994-09-01), Dermarkar et al.
patent: 5397918 (1995-03-01), Yokochi et al.
patent: 5747873 (1998-05-01), Talisa et al.
patent: 5798566 (1998-08-01), Sato et al.
patent: 5818105 (1998-10-01), Kouda
patent: 6054762 (2000-04-01), Sakuraba et al.
patent: 002260541 (1993-04-01), None
patent: 000543121 (1993-04-01), None
Horn Stuart B.
Nelson Elizabeth H.
Bashore Alain L.
Holford John E.
Lee Eddie C.
Lee Milton W.
Ortiz Edgardo
LandOfFree
Barrier layers for thin film electronic materials does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Barrier layers for thin film electronic materials, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Barrier layers for thin film electronic materials will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2531255