Barrier-free, low-resistant electrical contact on III-V semicond

Details Barrier-free, low-resistant electrical contact on III-V semicond Barrier-free, low-resistant electrical contact on III-V semicond

1981-03-17

1983-07-26

James, Andrew J.

357 65, 357 68, H01L 2348, H01L 2354, H01L 2940, H01L 2954

Patent

active

043957277

ABSTRACT:
A contact structure on indium-containing III-V semiconductor material is comprised of a four layer sequence consisting of an indium layer in direct contact with the semiconductor material, a zinc layer in contact with the indium layer, a chromium-nickel or chromium or palladium or platinum layer in contact with the zinc layer and a gold layer for external contacting with a lead. An exemplary embodiment of such contact structure exhibits specific contact resistance ranging between about 10.sup.-4 and 10.sup.-5 ohm.multidot. cm.sup.2.

REFERENCES:
patent: 4017332 (1977-04-01), James
"Evaporation Shielding for Continuous PbIn Deposition", Brunner, IBM Technical Disclosure Bulletin, vol. 19, No. 7, Dec. 1976, pp. 2496-2498.
"Ideal Ohmic Contacts to InP", Mills and Hartnagel, Electronics Letters, vol. 11, No. 25/26, pp. 621-622, Dec. 11, 1975, Institution of Electrical Engineers, London.
"Evaporation of Lead-Indium as Contacts for Semiconductor Chips", H. M. Dalal et al., IBM Technical Disclosure Bulletin, vol. 19, No. 5, Oct. 1976, p. 1677.

Affiliated with

Also associated with

Rating

Barrier-free, low-resistant electrical contact on III-V semicond does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Barrier-free, low-resistant electrical contact on III-V semicond, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Barrier-free, low-resistant electrical contact on III-V semicond will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2224360