Barrel shifter with parity bit generator

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36471508, 364 494, G06F 501, G06F 1110

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051445735

ABSTRACT:
A barrel shifter circuit is provided for use with the arithmetic and logic units of a computer. The circuit includes a generator of a parity word composed of parity bits, each associated with one of a plurality of groups of n bits, each group of n bits being obtained by partitioning input words A and B. The circuit also includes a parity matrix associated with a shift matrix for producing the parity bits of the groups of n consecutive bits that constitute an output word S, provided via parity output lines Q.

REFERENCES:
patent: 3045209 (1962-07-01), Pomerene
patent: 4462102 (1984-07-01), Povlick
patent: 4533992 (1985-08-01), Magar et al.
patent: 4556978 (1985-12-01), Kregness et al.
patent: 4839840 (1989-06-01), Tokumaru
patent: 4901263 (1990-02-01), Ho et al.
patent: 4999796 (1991-03-01), DeWitt et al.
Pseudo Nibble Parity for Fast Shifter Parity Predict IBM Tech. Disclosure Bulletin, vol. 31 No. 12 May 1989 pp. 262-266.

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