Barrel shifter using bit reversers and having automatic normaliz

Boots – shoes – and leggings

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364745, 364900, 36471508, G06F 700

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active

047824573

ABSTRACT:
A barrel shifter for a floating point processing unit can be optimized by having an automatic normalization feature. A multi-stage shifting unit is employed with external circuitry to verify that only leading zeros would be shifted out before activating a given shifting stage. Bit reversers are also used on the input and the output side of the barrel shifter in order to minimize the size and complexity of the circuit while still allowing bi-directional shifting.

REFERENCES:
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patent: 3961750 (1976-06-01), Dao
patent: 4181976 (1980-01-01), Collins et al.
patent: 4396994 (1983-08-01), Kang et al.
patent: 4472788 (1984-09-01), Yamazaki
patent: 4488252 (1984-12-01), Vassar
patent: 4583197 (1986-04-01), Chappell et al.
patent: 4636976 (1987-01-01), Takla
patent: 4665538 (1987-05-01), Machida
Weinberger, "Arithmetic Shift", IBM Technical Disclosure Bull., vol. 19, No. 1, Jun. 1976, pp. 207-216.
Gersback, "High-Speed Shifter Array", IBM Technical Disclosure Bull., vol. 21, No. 4, Sept. 1978, pp. 1379-1380.
Gersback, "Algebraic/Logical Shift Matrix" Technical Disclosure, Bull., vol. 23, No. 1, Jun. 1980, pp. 120-122.
Barrett, "Universal Shifter", IBM Technical Disclosure Bull., vol. 26, No. 12, May 1984, pp. 6341-6343.

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