Bare die multiple dies for direct attach

Details Bare die multiple dies for direct attach Bare die multiple dies for direct attach

1997-06-26

1998-08-04

Picard, Leo P.

Electricity: electrical systems and devices

Housing or mounting assemblies with diverse electrical...

For electronic systems and devices

361762, 361764, 361765, 361767, 361772, 361777, 361779, 361784, 361790, 257777, 257778, 257780, 257781, 257782, 257784, 257737, 257738, H05K 0100, H01L 2500

Patent

active

057903840

ABSTRACT:
A chip package includes a substrate formed from a first die and its attendant wiring interconnections, having a first thermal coefficient of expansion. The first die includes primary input/output (I/O) interconnections for the chip package. Also provided is a second die that includes escape wiring formed on that die and coupled to the primary I/O interconnections through the first die. The second die has a second thermal coefficient of expansion similar to the first thermal coefficient of expansion. The chip package also includes connectors that couple the primary I/O interconnections of the first die to a second level package. An interposer may be provided to couple the primary I/O interconnections to the second level package. The second die is smaller than the first die. The peripheral area of the first die is left exposed when the second die is coupled to the first die so that sufficient I/O interconnections may be formed for the primary I/O interconnections on the first die. The second die provides and receives signals which may include the second die's primary I/O to and from the first die. Wiring may be shared between the first die and the second die in a manner optimal for design and manufacturing.

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