Static information storage and retrieval – Addressing – Plural blocks or banks
Reexamination Certificate
2000-06-30
2001-08-21
Nelms, David (Department: 2818)
Static information storage and retrieval
Addressing
Plural blocks or banks
C365S104000, C365S072000
Reexamination Certificate
active
06278649
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to high density, integrated circuit memory devices including flat cell ROM, and more particularly to structures for coupling banks of memory cells to array bit lines in which there are a plurality of columns of memory cells sharing each array bit line.
2. Description of Related Art
High-density integrated circuit memory designs often have an architecture that includes array bit lines, often called global bit lines, that extend across an array, and a number of shorter bank bit lines, often called local bit lines, that extend parallel to the array bit lines across a bank of memory cells in the array. For example, a bank bit line may extend across 32, 64 or 128 rows of memory cells in an array. Bank bit lines are typically implemented as diffusion regions in the substrate of the integrated circuit, and act as a source or drain for the memory cells to which they are coupled. The array bit lines are typically implemented as metal lines which extend over the array. Metal to diffusion contacts act as connection points for coupling the bank bit lines to the array bit lines. Bank select circuits are operated to connect a bank bit line to an array bit line in order to access a given memory cell on the bank bit line.
In the design of the bank select circuits, a number of factors is involved. The number of transistors through which the cell current must past through before connection with the array bit line affects the speed of operation of the device. The flexibility by which a given bank bit line may be coupled to one or more array bit lines affects the manner in which the individual cells may be accessed. Also, the design of the bank select circuits has a direct impact on the layout of the memory array. The bank select circuitry also determines whether a given bank bit line may be connected to ground or to a sense amplifier through array bit lines which may be dedicated to one or the other. Finally, the bank select circuitry may also limit the number of columns of memory cells which may be simultaneously coupled to sense amplifiers for high-speed, page mode implementations.
The prior art in this field includes U.S. Pat. No. 5,241,497; U.S. Pat. No. 5,117,389; U.S. Pat. No. 5,392,233; U.S. Pat. No. 5,812,440; and U.S. Pat. No. 5,392,233; and a large number of other references. A review of the bank selection circuitry for these prior art patents shows deficiencies in density, sensing speed or sensing flexibility of the prior art.
In modern memory design, such as for high-density, flat cell mask ROM for which speed of access is critical, the flexibility of the bank select structure becomes more critical. The bank select structure must involve as few transistors in the sensing path as possible to insure highest speed access to the data. Furthermore, in some designs, the number of array bit lines dedicated to ground terminals is reduced, and the need to share a ground line by more than one sense amplifier has arisen. Thus, the bank select structure must support the use of multiple sense amplifiers with a shared ground line, flexibility in the selection of memory cells to be accessed, high speed operation, and other aspects of high-density memories.
SUMMARY OF THE INVENTION
The present invention provides an integrated circuit memory having bank select circuitry that is suitable for high-density, high-speed memory such as flat cell mask ROM devices. The bank select circuitry is based on bank select transistors which allow for independently connecting, individually and in combination, the array bit lines with bank bit lines, while relying on a small number of transistors in the sensing path.
Thus, the present invention provides an integrated circuit memory that comprises an array of memory cells arranged in rows and columns, and including a plurality of banks. There are a plurality of word lines along the plurality of rows in the array, and a plurality of array bit lines arranged along the plurality of columns. The memory cells are non-volatile cells, a flat cell mask ROM in various embodiments of the invention. The array bit lines extend across the array, and include sense lines and ground lines. A plurality of bank bit lines is arranged along the plurality of columns. The bank bit lines extend across corresponding banks in the plurality of banks and are coupled to memory cells in the corresponding banks. A plurality of connection terminals are coupled to the array bit lines. For each array bit line there is at least one connection terminal per bank in the plurality of banks for which the array bit line will be used. A plurality of bank select transistors is provided to act as bank select circuitry. The bank select transistors are operable to selectively connect respective bank bit lines to corresponding connection terminals for array bit lines. The bank select transistors are characterized by allowing independent connection of bank bit lines to sense lines of the plurality of array bit lines, while minimizing the number of transistors in the sensing path. In another aspect, the bank select transistors allow independent connection of the bank bit lines to both sense lines and ground lines in the plurality of array bit lines.
Accordingly, the bank selection circuitry includes for a first particular connection terminal in the plurality of connection terminals on particular sense line and within a particular bank, bank select transistors coupled to the first particular connection terminal, and local bit line select lines coupled to the bank select transistors, by which a bank bit line LBx and a bank bit line LBx+2 are independently connectable to the particular sense line, and a bank bit line LBx+1 is connectable to the particular sense line. For a second particular connection terminal on a particular ground line and within the particular bank, the bank select transistors are coupled to the second particular connection terminal and to local ground select lines. The bank bit line LBx and the bank bit line LBx−2 are independently connectable to the particular ground line, and the bank bit line LBx−1 is connectable to the particular ground line as well.
According to one aspect of invention, each of the connection terminals is associated with three bank select transistors and three local bit line select lines. Thus for example for the first particular connection terminal in this aspect of invention there are three bank select transistors and three local bit line select lines by which the bank bit line LBx, the bank bit line LBx+1 and the bank bit line LBx+2 in the plurality of bank bit lines are independently connectable to the particular sense line. Likewise, for the second particular connection terminal there are three bank select transistors and three local ground select lines by which the bank bit line LBx, the bank bit line LBx−1 and the bank bit line LBx−2 in the plurality of bank bit lines are independently connectable to the particular ground line. This provides for independent connection of the bank bit lines to sense lines or ground lines for use as ground lines, sense lines or shielding lines during the reading of data from the device, or during other operations.
According to yet another aspect of invention, the bank select circuitry supports using fewer array bit lines as dedicated ground. In this aspect, for the second particular connection terminal on the particular array bit line, additional bank select transistors are coupled to the second particular connection terminal and additional local ground select lines are coupled to the additional bank select transistors. In this manner, the bank bit line LBx+2 and the bank bit line LBx+4 are independently connectable to the particular ground line, and the bank bit line LBx+3 is connectable to particular ground line. In a preferred implementation, for the second particular connection terminal, there are 6 local ground select lines and 6 bank select transistors by which the bank bit line LBx, the bank
Lee Yu-Wei
Yang Nien-Chao
Haynes Mark A.
Haynes & Beffel LLP
Lam David
Macronix International Co. Ltd.
Nelms David
LandOfFree
Bank selection structures for a memory array, including a... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Bank selection structures for a memory array, including a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Bank selection structures for a memory array, including a... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2540754