Bank selection signal control circuit for use in...

Details Bank selection signal control circuit for use in... Bank selection signal control circuit for use in...

2007-10-30

2007-10-30

Elms, Richard T. (Department: 2824)

Static information storage and retrieval

Addressing

Plural blocks or banks

C365S233100

Reexamination Certificate

active

11270899

ABSTRACT:
Memory bank selection control circuits and methods are provided which improve the data sensing margin for data sense amplifiers in a multi-bank semiconductor memory structure. In one aspect, a bank selection signal control circuit includes a bank switch control unit that receives memory bank selection signals and outputs corresponding memory bank selection control signals to selectively connect memory banks to a global data input/output line according to a predetermined sequence. For memory bank selected prior to a last selected memory bank in the predetermined sequence, the bank switch control unit outputs memory bank selection control signals that are enabled for a first time period P1, and for the last selected memory bank, the bank switch control unit outputs a memory bank selection control signal that is enabled for a second time period P2, wherein P2is greater than P1. A switching unit sequentially connects each selected memory bank to the global data input/output line according to the predetermined sequence, and for a predetermined period P1or P2, in response to the corresponding bank selection control signals.

REFERENCES:
patent: 7180807 (2007-02-01), Park
patent: 2002/0105635 (2002-08-01), Koshikawa
patent: 2003/0067834 (2003-04-01), Lai

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