Patent
1995-06-06
1998-04-07
Swann, Tod R.
395405, G06F 1200
Patent
active
057375720
ABSTRACT:
A system and method for controlling DRAM is described. According to exemplary embodiments of the present invention, a memory subsystem can be populated by end users with any of a variety of DRAM chips. A memory controller will size each memory bank and determine whether paired memory banks are to be configured as interleaved or non-interleaved based upon the detected DRAM population. Bank selection logic is designed to account for both size and status (interleaved or non-interleaved) when determining which memory bank contains a memory location of interest. Row and column addressing is selected to minimize decoding of an incoming system address and reduce DRAM access time.
REFERENCES:
patent: 4924375 (1990-05-01), Fung
patent: 4926314 (1990-05-01), Dhuey
patent: 5040153 (1991-08-01), Fung
patent: 5179686 (1993-01-01), White
patent: 5241643 (1993-08-01), Durkin
patent: 5269010 (1993-12-01), MacDonald
patent: 5278801 (1994-01-01), Dresser et al.
patent: 5301278 (1994-04-01), Rowater
patent: 5303364 (1994-04-01), Mayer et al.
patent: 5307320 (1994-04-01), Farrer et al.
patent: 5341494 (1994-08-01), Thayer et al.
patent: 5353423 (1994-10-01), Hamid et al.
patent: 5371866 (1994-12-01), Cady
patent: 5375084 (1994-12-01), Begun
patent: 5386383 (1995-01-01), Raghavachari
patent: 5572692 (1996-11-01), Murdoch
AM29022.TM. RISC Microcontroller User's Manual and Data Sheet, pp. 9-1 thru 9-10 (Chapter 9, DRAM Controller) 1991.
Apple Computer Inc.
Chow Christopher S.
Swann Tod R.
LandOfFree
Bank selection logic for memory controllers does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Bank selection logic for memory controllers, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Bank selection logic for memory controllers will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-25112