Bank selection for synchronous readable and writable semiconduct

Details Bank selection for synchronous readable and writable semiconduct Bank selection for synchronous readable and writable semiconduct

1997-03-24

1999-09-14

Nelms, David C.

Static information storage and retrieval

Addressing

Plural blocks or banks

36518511, G11C 800

Patent

active

059532807

ABSTRACT:
In a synchronous DRAM having a memory cell array which is constituted of first to fourth memory banks but which can be selectively operated either in a 2-bank structure or in a 4-bank structure, a bank control signal generating unit receives external active command signals including a RAS command signal, a CAS command signal, a WE command signal and the CS command signal, and external bank selection signals, for generating first to fourth read/write bank selection signals and first to fourth bank activation signals. An address signal generating unit receives external address signals, for generating an internal row address signal and an internal column address to the memory cell array. The bank control signal generating unit is configured to selectively operate at least one memory bank in a data read/write operation without receiving an external bank switching signal having a function of switching the number of memory banks.

REFERENCES:
patent: 5469391 (1995-11-01), Haraguchi
patent: 5535169 (1996-07-01), Endo et al.
patent: 5553026 (1996-09-01), Nakai et al.
"A 150MHz 8-Banks 256M Synchronous DRAM with Wave Pipelining Methods"; Yoo et al 1995 IEEE International Solid-State Circuites Conference; Feb. 17, 1995; pp. 250-251.

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