Static information storage and retrieval – Read only systems – Semiconductive
Reexamination Certificate
2001-06-15
2002-05-14
Nelms, David (Department: 2818)
Static information storage and retrieval
Read only systems
Semiconductive
C365S185110, C365S182000, C365S104000, C257S390000, C257S314000, C438S128000
Reexamination Certificate
active
06388911
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to semiconductor integrated circuits and more particularly to a bank select structure layout of a high density read only memory circuit.
BACKGROUND OF THE INVENTION
Read-only memory (ROM) is a nonvolatile semiconductor memory widely used in computer and microprocessor systems for permanently storing information including programs and data that will be repeatedly used. ROM manufacturing involves very complicated and time-consuming processes and require costly equipment and material. Therefore, the data that is to be permanently stored in ROM's are first defined by the customer and then furnished to the factory to be programmed into the ROM.
Most ROM are identical in semiconductor structure except for the different values of data stored therein. Therefore, the ROM devices can be fabricated up to the stage ready for data programming and then the semi-finished products are stocked in inventories waiting for customer orders. The customer then furnishes the data to the factory where the data is stored into the semi-finished ROM by using, the commonly called mask programming process. This procedure is presently a standard method in the semiconductor industry for fabricating ROM.
Conventional ROM are usually based on metal-oxide semiconductor field-effect transistor (MOSFET) memory cells, each memory cell is used for the storage of one value of the binary-coded data, “0” or “1”. In the mask programming process, these MOSFET-based memory cells are selectively doped with impurities into the associated channel regions to change the threshold voltage. Supposing a memory cell is in a permanently-ON state when applying a 5v voltage on it represents the permanent storage of the binary-coded data, for example “0”, and the memory cells is a permanently-OFF state represents the permanent storage of the binary-coded data, for example 1.
FIG. 1
shows a circuit configuration layout pattern of a memory cell array of a mask ROM. In
FIG. 1
, the vertical bit lines
101
are formed by an N conductive type buried diffusion layer, and the horizontal word lines
102
are formed by a polycide. The bit lines
101
and the word lines
102
are arranged to intersect each other. The memory cell transistors
103
are formed in such a way that the source and drain regions are formed at the intersecting portions, and the channels are formed between the intersecting portions. The memory cell transistors
103
are coded by an impurity diffusion technique into the channels. Each memory cell transistor
103
is formed to be turned on or off on the basis of a predetermined gate voltage according to whether an information bit is to be held by the cell.
In the memory cell array shown in
FIG. 1
, the bank select
104
,
105
are also shown, wherein the bank select
104
is up bank select and the bank select
105
is down bank select. Each bank select is composed of 2 select bit lines
106
,
107
and
108
,
109
. The up select bit lines
106
and
107
and buried bit lines and main bit lines
115
,
116
and
117
are arranged to intersect each other. The up select transistors
110
and
112
are formed in such a way that the source and drain regions are formed at the intersecting portions, and the channels are formed between the intersecting portions. The down select bit lines
108
and
109
and buried bit lines and ground bit lines
118
and
119
, they are arranged to intersect each other. The down select transistors
113
and
114
are formed in such a way that the source and drain regions are formed at the intersecting portions, and the channels are formed between the intersecting portions. When reading the data stored in memory cell
103
, a high voltage is applied to the up select bit line
106
and down select bit line
108
to open the up select transistor
110
and down select transistor
113
. Therefore, there is a formed current path starting from the main bit line
116
to pass through the up select transistor
110
, the buried bit line
120
, the memory cell
103
, the buried bit line
121
and the down select transistor
113
, and then to reach the ground bit line
119
connected to the ground to finish the reading data work.
One major drawback to the foregoing ROM device, however, is that the code-implantation process requires a threshold voltage change and code-implantation process is also performed on the up bank select and the down bank select so as to close these select transistors not being used during operation. Referring to
FIG. 1
, the block diagram
130
to
137
in the figure is the code-implantation region for raising the threshold voltage of the select transistor in the region. Typically, the substrate of conventional ROM is P type and the buried bit lines, main bit lines and ground bit lines are N type. Then, the P type impurity is used as the ion source to implant the impurity to diffuse into the channels. The overlapping situation usually happens during the implantation process, which will cause the source and drain's concentration decrease of these select transistors performed implantation process. Under this condition, the junction leakage current will increase. Some of the main bit lines and ground bit lines also overlaps during the performing implantation process in this kind of structure layout pattern, and if the voltage is applied on the main bit line, the junction leakage current will also increase and cause an overlap.
SUMMARY OF THE INVENTION
With these foregoing structure layout pattern problems, it is the objective of the present invention to provide a new ROM structure layout pattern design. Under the new layout pattern design, the main bit lines and the ground bit lines may not overlap during the performed implantation process. The main bit lines and the ground bit lines may not be affected by the performed implanting process, therefore, the junction leakage current will not be increased.
To achieve the above-mentioned objective, the present invention provides a ROM having a plurality of memory cell blocks, each composed of a main bit line, a ground bit line, and a plurality of memory cells for storing information, which comprises: a plurality of up select transistors for selecting a memory cell block connected to the main bit line from a memory cell block plurality; and a plurality of down select transistors for selecting a memory cell block connected to the ground line from a plurality of the memory cell blocks, said up select transistors and down select transistors being arranged alternately with the memory cell block in between, wherein the layout pattern of said up select transistors and down select transistors has been rotated 90 degrees. Under this kind of new layout pattern, the main bit lines and the ground bit lines will not be affected by the process of ion implantation process, therefore, the junction leakage current will not be increased.
REFERENCES:
patent: 5379254 (1995-01-01), Chang
patent: 5590068 (1996-12-01), Bergemont
patent: 5933735 (1999-08-01), Wen
Ho Tu-Tu
Macronix International Co. Ltd.
Nelms David
LandOfFree
Bank select structure layout of read only memory without the... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Bank select structure layout of read only memory without the..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Bank select structure layout of read only memory without the... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2840713