Bandwidth and frame buffer size reduction in a digital pulse-wid

Computer graphics processing and selective visual display system – Computer graphic processing system – Plural graphics processors

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345509, 345210, 395116, G09G 334

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active

060644044

ABSTRACT:
A method and apparatus are used for converting a stream of incoming serial video data which is received frame by frame and is formatted with all data bits arriving together for each pixel into digital PWM video formatted as a sequence of like-weighted bits. Incoming video data is temporarily stored in a digital memory. A controller organized the data in the memory into a plurality of buffers, each buffer having only bits of like weight. The data is collected as groups within the buffers. The data is then coupled to a display device as the groups of like-weighted bits after a predetermined fraction of a frame time for producing the desired PWM signal. Since each bit of the incoming video data is stored for a fraction of a frame time, the present invention facilitates decimation of the total amount of buffer memory, compared to that of the prior art. A method of and apparatus are used for converting a stream of incoming serial PWM video data which is received frame by frame and is organized with all data for a single pixel transmitted concurrently into digital PWM video organized into groups of like-weighted bits. Once the stream of incoming serial PWM video data is received it is stored in a digital memory. A controller organized the data in the memory into a plurality of bit planes, each bit plane having only bits of like weight. The data is collected as groups within the bit planes. The data is coupled to a display device as groups of like-weighted bits. As groups of the shortest duration bit weight are formed, they are coupled to the display. This allows less than an entire frame of data to be stored.

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