Bandgap using lateral PNPs

Details Bandgap using lateral PNPs Bandgap using lateral PNPs

2002-10-15

2004-08-03

Nguyen, Matthew V. (Department: 2838)

Electricity: power supply or regulation systems

Self-regulating

Using a three or more terminal semiconductive device as the...

C327S539000

Reexamination Certificate

active

06771055

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to voltage reference circuits, and more particularly to CMOS bandgap voltage reference circuits.
BACKGROUND OF THE INVENTION
Most CMOS bandgap circuits use a variation of the Brokaw topology, an example of which is shown in FIG.
1
.
FIG. 1
is a schematic of a conventional Brokaw bandgap voltage reference circuit (
100
). Circuit
100
is subject to undesirable variances in the offset voltage of the inputs for the operational amplifier. In CMOS processes the offset voltage can be on the order of 10 mV. Such large voltage offsets can result even if the input devices are drawn to large scales on the order of 100 &mgr;m. The ratio of transistor Q
2
to Q
1
can be made large, but this would result in a &Dgr;VBE of only 100 mV. A voltage offset of 10 mV equates to a 10% error.
A second problem associated with conventional bandgap reference voltages is associated with the size of transistor Q
1
. Transistor Q
1
is typically selected to be relatively small, which results in a desirably large ratio of transistor Q
2
to Q
1
. However, the relatively small size of transistor Q
1
typically results in the VBE of the transistor being subject to variances in manufacturing processes. The variances in the VBE undesirably affect the accuracy of the output voltage of bandgap circuit
100
.
SUMMARY OF THE INVENTION
According to one aspect of the invention, a CMOS circuit for generating a bandgap voltage reference is provided. The CMOS circuit comprises a first bipolar transistor, an operational amplifier, and a resistive network. The first bipolar transistor is configured to generate a VBE reference. The operational amplifier has a first and a second lateral PNP transistor. The first and second lateral PNP transistors are configured to generate a &Dgr;VBE reference. The resistive network is configured to produce a bandgap voltage reference in response to the generated VBE reference and the generated &Dgr;VBE reference.
According to another aspect of the invention, a method for generating a bandgap voltage in a CMOS circuit comprises generating a VBE reference by using the base-emitter voltage of a first transistor. A &Dgr;VBE reference is generated by using first and second lateral PNP transistors as the input stage of an operational amplifier. The bandgap voltage reference is produced in response to the generated VBE reference and the generated &Dgr;VBE reference.
A more complete appreciation of the present invention and its improvements can be obtained by reference to the accompanying drawings, which are briefly summarized below, to the following detailed description of illustrated embodiments of the invention, and to the appended claims.


REFERENCES:
patent: 5796244 (1998-08-01), Chen et al.
patent: 6181196 (2001-01-01), Nguyen
patent: 6232756 (2001-05-01), Kurihara
patent: 6294902 (2001-09-01), Moreland et al.
patent: 6529066 (2003-03-01), Guenot et al.
patent: 6630859 (2003-10-01), Wang

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