Bandgap reference circuit for charge balance circuits

Details Bandgap reference circuit for charge balance circuits Bandgap reference circuit for charge balance circuits

1999-07-07

2001-11-27

JeanPierre, Peguy (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

C307S402000, C341S143000

Reexamination Certificate

active

06323801

ABSTRACT:

BACKGROUND OF THE INVENTION
This invention relates generally to bandgap reference circuits and more particularly to bandgap reference circuits adapted for use in charge balance circuits.
As is known in the art, bandgap reference circuits have widespread use in integrated circuits to provide a reference voltage which is substantially invariant with temperature. The original integrated circuit bandgap reference circuit used bipolar transistors. One such circuit is described in “A Simple Three-Terminal IC Bandgap Reference”, by A. P. Brokow, published in IEEE Journal of Solid-State Circuits, vol. SC-9, pp. 388-393, December 1974.
More recently, CMOS technology has been in use for digital circuits and such CMOS circuits frequently require a CMOS bandgap reference circuit. One example of such a circuit is presented in a paper entitled “A Precision CMOS Bandgap Reference”, by J. Michejda and S. K. Kim, published in IEEE Journal of Solid-State Circuits, vol. SC-19, no. 6, pp. 1014-1021, December 1984. Such circuit is shown in FIG.
1
and includes a pair of diode-connected bipolar transistors Q
1
and Q
2
, the transistor Q
1
having N times the number of emitters of (i.e., N times the emitter area of) transistor Q
2
, where N is an integer greater than 1. It is noted that a diode-connected transistor provides a p-n junction between the emitter and base terminals thereof, with the collector terminal shorted to the base. These transistors Q
1
and Q
2
are provided by the substrate bipolar transistor (in this case, p-n-p) that are a by-product of the CMOS process. They are not generally of the same quality as the transistors available in a true bipolar or biCMOS process. In particular, the current gain, beta, and Early voltage, V
A
, are poorer. The basic idea is to produce a base-emitter voltage V
BE
and have added to it a multiple G of a voltage &Dgr;V
BE
such that the sum, V
BE
+G&Dgr;V
BE
, is a reference voltage which is substantially invariant with temperature.
More particularly, an operational amplifier A
1
is provided with a resistor R
2
connected between the output of amplifier A
1
and the inverting (−) input of the amplifier. The inverting input (−) is coupled to ground through a resistor R
1
and the diode-connected transistor Q
1
. The non-inverting input (+) of amplifier A
1
is connected to ground through the diode-connected transistor Q
2
and to the output of amplifier A
1
through the resistor R
3
. The feedback arranged amplifier A
1
drives the junction between resistors R
1
and R
2
to the same voltage as the voltage at the emitter of transistor Q
2
. With R
2
=R
3
, the current through the diode-connected transistor Q
1
will be driven to the same value as the current through the diode-connected transistor Q
2
. However, because of the larger emitter area of transistor Q
1
, transistor Q
1
will have a smaller V
BE
than that of transistor Q
2
. Thus, &Dgr;V
BE
, appears across resistor R
1
and the output voltage V
REF
of the amplifier may be expressed as:
V
REF
=V
BE
+(1+
R
2
/R
1
)&Dgr;
V
BE
=V
BE
+G&Dgr;V
BE
where &Dgr;V
BE
=V
T
ln(N)=(kT/q)ln(N), k is Boltzman's constant, T is temperature in degrees Kelvin and q is the charge of an electron.
Typically, at 300° K., V
BE
has a value of about 650 mV and a temperature coefficient of −2 mV/° K. V
T
has a value of 25.9 mV and a temperature coefficient of +86.2 &mgr;pV/° K. For a typical value N of 8, &Dgr;V
BE
will therefore have a value of 53.8 mV and a temperature coefficient of +179.2 &mgr;V/° C. To balance the large negative temperature coefficient of V
BE
, G should be 11.2. That is, R
2
/R
1
=10.2. In such case, V
REF
=0.65+{11.2×0.0538}=1.25 V.
The main limitation to performance achievable by CMOS bandgap circuits is not the substrate bipolars but the poor offset and low frequency noise (1/f) of the CMOS amplifier, A
1
. The noise and offset are represented by the voltage source V
OS
in FIG.
1
. The noise and offset add directly to &Dgr;V
BE
and therefore see the same high gain G, here 11.2 to the output V
REF
. Thus, the V
REF
, including the effect of noise and offset, (i.e., V
OS
) may be represented as:
V
REF
=V
BE
+[1+(
R
2
/R
1
)][&Dgr;
V
BE
+V
OS
].
Another approach to bandgap reference design is the use of a switched capacitor amplifier as shown in FIG.
2
and discussed in U.S. Pat. No. 5,059,820, issued Oct. 22, 1991, entitled “Switched Capacitor Bandgap Reference Circuit Having Time Multiplexed Bipolar Transistor”, inventor A. L. Westwick. Here, the basic idea is that V
BE
and &Dgr;V
BE
voltages are sampled on capacitors C
1
and C
2
, respectively, and combined in the correct proportion to form a substantially temperature invariant reference voltage V
REF
. More particularly, a pair of current sources
12
,
14
are connected to inputs of switches S
1
and S
2
respectively, the outputs of such switches being connected to the emitter of diode-connected transistor Q
1
. The current produced by current source
12
is I and the current produced by current source
12
is nI, where n is an integer greater than one. Switches S
2
and S
3
close and switches S
1
and S
4
open during a first of two phases, (i.e., switches S
2
and S
3
close during the first phase when pulse P
1
, shown in
FIG. 3
, is “high” and switches S
1
and S
4
open during the first phase when pulse P
2
is “low”). Switches S
2
and S
3
open and switches S
1
and S
4
close during a second of the two phases, (i.e., switches S
2
and S
3
open during the second phase when pulse P
1
, shown in
FIG. 3
, is “low” and switches S
1
and S
4
close during the second phase when pulse P
2
is “high”). In operation, during the first phase, current nI flows through Q
1
and during the second phase current I flows through transistor Q
1
producing, during the second phase, a smaller V
BE
at the emitter of transistor Q
1
. The difference in V
BE
produced at the emitter of Q
1
(i.e., &Dgr;V
BE
) is sampled by capacitor C
2
and charge corresponding to the sampled difference in V
BE
is transferred to capacitor C
3
during the second phase. Meanwhile, capacitor C
1
samples the V
BE
produced at the emitter of transistor Q
1
during the first phase and transfers charge corresponding to this sampled V
BE
to capacitor C
3
during the second phase. It is noted that the capacitor C
3
is shunted by switch
16
which closes when pulse P
3
goes “high”, shown in
FIG. 3
, and opens when pulse P
3
goes “low”, such pulse P
3
being shown on a common time base with the pulses P
1
and P
2
in FIG.
3
. The expression for the voltage produced at the output of amplifier A
1
during the second phase (i.e., when pulse P
2
is “high”, as shown in
FIG. 3
) may be expressed as:
V
REF
=[C
1
/
C
3
]
V
BE
+[C
2
/
C
3
]&Dgr;
V
BE
which may alternatively be expressed as:
V
REF
=[C
1
/
C
3
][
V
BE
+(
C
2
/
C
1
)&Dgr;
V
BE
],
where now
&Dgr;V
BE
=V
T
ln(n).
It is noted that the ratio of C
2
/C
1
is similar in function to the scale factor G described above in connection with FIG.
1
. Thus, the ratio C
2
/C
1
is selected so that V
REF
is substantially invariant with temperature. Further, the ratio C
1
/C
3
adds additional freedom to enable V
REF
to be scaled larger or smaller than the bandgap voltage as required. Furthermore, the &Dgr;V
BE
is now set by a current ratio, n, rather than by an emitter ratio, N.
If the amplifier A
1
, in
FIG. 2
, has an offset V
OS
, then it is possible to show that the second phase voltage is
V
REF
=V
OS
+[C
1
/
C
3
][
V
BE
+(
C
2
/C
1
)&Dgr;
V
BE
].
The offset voltage receives much less gain than in the previous linear bandgap reference voltage circuit described above in FIG.
1
. It is to be noted, however, that the charge injection at the falling edge of pulse P
3
will still add an error to V
REF
.
One application of a b

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