Band-gap reference circuit

Details Band-gap reference circuit Band-gap reference circuit

2000-11-17

2002-03-12

Berhane, Adolf Deneke (Department: 2838)

Electricity: power supply or regulation systems

Self-regulating

Using a three or more terminal semiconductive device as the...

C323S314000, C327S539000

Reexamination Certificate

active

06356064

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a band-gap reference circuit. In particular, it relates to a band-gap reference circuit with a start-up circuit attached.
2. Description of the Related Art
Japanese Patent Application Laid-open No. Hei 8-186484 discloses a band-gap reference circuit containing a start-up circuit, which is used to reduce the amount of time that elapses from when the power source voltage is first supplied until a stable operating state is attained in the band-gap reference circuit, which generates a stable (in terms of temperature change), predetermined standard voltage and which operates basically in the PN junction band-gap region.
FIG. 1
shows the conventional circuit disclosed in Japanese Patent Application Laid-open No. Hei 8-186484.
The conventional band-gap reference circuit is comprised of a band-gap circuit
10
, which generates and outputs the pre-determined, standard voltage V
REF
during the active state; and a start-up circuit
20
, which reduces the time elapsing from when the power source is first applied up to it reaching a stable operating state.
Band-gap circuit
10
is comprised of P-channel MOS transistor (PMOS)
11
, which has its source connected to power source V
DD
(the high voltage side) and has its gate and drain connected to each other and also connected to node A; N-channel MOS transistor (NMOS)
12
, which has its drain connected to the drain of PMOS
11
; first resistor
13
, which has one terminal connected to the source of NMOS
12
and the other terminal connected to the ground (the low voltage side of the power source); PMOS
14
, which has its source connected to power source V
DD
and its gate connected to the drain of PMOS
11
; and NMOS
15
, which has its drain connected to its gate, and to the drain of PMOS
14
and gate of NMOS
12
and also connected to node B, and which has its source connected to the ground. Band-gap circuit
10
is further comprised of PMOS
16
, which has its source connected to power source V
DD
, its gate to node A, and has its drain as a standard voltage output terminal; second resistor
17
, which has one terminal connected to the drain of PMOS
16
; and diode
18
, which has its anode connected to the other terminal of second resistor
17
and its cathode connected to the ground.
According to the Japanese Patent Application Laid-open Hei 8-186484 mentioned above, the reference voltage output V
REF
when band-gap circuit
10
is in a stable operating state can be given as the following equation:
V
REF
=N
·(
k·T/q
)·ln
M+VF
  (1)
where N is the ratio of the resistance value of the first resistor
13
over the resistance value of the second resistor
17
; k is Boltzmann constant; T is absolute temperature; q is the electron charge; M is the ratio of the gate width of NMOS
12
over the gate width of NMOS
15
; VF is the forward bias across diode
18
. In order to prevent an occurrence of changes in the characteristics of each transistor due to manufacturing irregularities, the each respective channel length of PMOS
11
, PMOS
14
, PMOS
16
, NMOS
12
, and NMOS
15
should be at least 10 &mgr;m, with the range of 50 &mgr;m to 100 &mgr;m being most preferable.
Start-up circuit
20
is made up of PMOS
21
, which has its source connected to power source V
DD
; PMOS
22
, which has its source also connected to power source V
DD
, and which also has its gate connected to the drain of PMOS
21
forming node C; third resistor
23
, which has one terminal connected to node C and the other terminal connected to the ground; and capacitor
24
, which has one terminal connected to node C and the other terminal connected to the ground. Signal S
1
output from node A of band-gap circuit
10
is input to the gate of PMOS
21
, and the drain of PMOS
22
is connected to node B in band-gap circuit
10
.
FIG. 2
is an operational timing graph for the conventional circuit at the time when power is first supplied. The workings of the conventional band-gap reference circuit at the time when power is first applied will now be described in detail while referencing FIG.
2
.
As shown in
FIG. 2
, it is assumed that power source voltage V
DD
starts at nearly 0 V climbing up to 3.3 V. When power source voltage V
DD
is first supplied, which is shown in
FIG. 2
as the time-frame from time-point t
1
to t
2
, since the source of PMOS
11
is the voltage level equal to V
DD
and its gate is nearly ground level (0 V), the voltage difference between the gate and source of PMOS
11
is smaller than its threshold voltage V
tp1
of PMOS
11
in terms of their absolute values. This causes the transistor to turn off. Also, since the voltage levels at the source and gate of PMOS
21
are the same as the respective voltage levels at the source and gate of PMOS
11
, PMOS
21
is also turned off and accordingly, node C is at ground level.
When power source voltage V
DD
continues to appreciate past time-point t
2
, the voltage difference between the gate and source of PMOS
11
becomes larger than the threshold voltage V
tp1
of PMOS
11
in terms of their absolute values. This causes PMOS
11
to turn on, and node A rises keeping pace with power source voltage V
DD
, while maintaining a difference of roughly V
tp1
lower than V
DD
. In the same manner, when PMOS
21
is also turned on, the voltage level at node C in start-up circuit
20
begins to appreciate at a remarkably slow rate when compared to the rise in the power source level V
DD
due to resistor
23
and capacitor
24
.
At this point, when all of the PMOS transistors in both band-gap circuit
10
and start-up circuit
20
have the same channel lengths and the same threshold voltage V
tp1
, if the voltage difference between the power source voltage V
DD
and node C continues to become larger than V
tp1
, in terms of their absolute values, past time-point t
2
, then the charging of node B is accelerated because PMOS
22
will also be turned on.
At time-point t
3
, due to the rising voltage level at node B, the gate voltage of NMOS
12
and NMOS
15
surpasses the threshold voltage V
tn
and they are turned on. As a result, the increase in voltage level at node A temporarily stagnates. Accordingly, the difference between the voltage levels of the gate and source of PMOS
21
surges, turning PMOS
21
on deeply. Moreover, because the PMOS transistor being utilized for PMOS
21
has an extremely large channel width that is hundreds of times larger than that of PMOS
11
, at time-point t
4
the voltage level of node C comes under the influence of power source voltage V
DD
and begins a rapid ascent. Then since PMOS
22
turns off as the voltage level of node C approaches that of power source voltage V
DD
, start-up circuit
20
becomes electrically isolated from band-gap circuit
10
. Once power source voltage V
DD
stabilizes at its predetermined voltage level (e.g., 3.3 V in FIG.
2
), terminals A and B of band-gap circuit
10
, as well as output reference voltage V
REF
stabilize at their respective pre-determined voltages.
With the band-gap reference circuit with an attached start-up circuit as shown in
FIG. 1
, when power source voltage V
DD
is first applied, node B in band-gap circuit
10
momentarily has more charge than start-up circuit
20
. As a result, it is possible for a band-gap circuit without the start-up circuit to reach its stable state in a very short time compared to when node B is charged with only the very small amount of current flowing through PMOS
14
.
In this conventional band-gap reference circuit, however, the start-up circuit requires an enormous amount of exclusive space since the channel width of PMOS
21
within the start-up circuit must be large, and demands have been made for a reduction in this required surface area. In accordance with these demands, if the channel length of PMOS
21
is reduced by a factor of 1
compared to the other PMOS transistors then it is possible to reduce the channel width by the same factor of 1
; therefore the required space for th

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