Ballast resistors with parallel stacked NMOS transistors used to

Details Ballast resistors with parallel stacked NMOS transistors used to Ballast resistors with parallel stacked NMOS transistors used to

1998-07-13

2000-03-28

Jackson, Stephen

Electricity: electrical systems and devices

Safety and protection of systems and devices

Transient responsive

361 56, 361 58, 361118, H02H 900

Patent

active

060439696

ABSTRACT:
Electrostatic discharge (ESD) protection is provided for NMOS pull up transistors 700A-H and 702A-H of a 5.0 volt compatible output buffer using 2.5 volt process transistors. The ESD protection includes ballast resistors 701A-H and 703A-H separating individual pairs of NMOS pull up transistors 700A-H and 702A-H from the pad and from a power supply connection NV3. The ballast resistors enable turn on of additional pairs of NMOS pull up transistors after a first pair, such as 700A,702A turns on during an ESD event to prevent secondary breakdown in the first NMOS pair. Pairs of NMOS pull up transistors are used to prevent voltages across individual NMOS transistors from exceeding a 2.7 volt maximum while still enabling the transistors to provide 5.0 volts to the pad.

REFERENCES:
patent: 4990802 (1991-02-01), Smooha
patent: 5510728 (1996-04-01), Huang

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