Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Bump leads
Reexamination Certificate
2002-01-30
2003-04-22
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Bump leads
C257S678000, C257S690000, C257S693000, C257S784000
Reexamination Certificate
active
06552430
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to ball grid array substrates having traces formed from a copper-based metal. In one aspect, it relates to micro ball grid array integrated circuit packages.
BACKGROUND
Integrated circuits are usually formed on semiconductor wafers. The wafers are separated into individual chips and the individual chips are then handled and packaged. The packaging process is one of the most critical steps in the integrated circuit fabrication process, both from the point of view of cost and of reliability. Specifically, the packaging cost can easily exceed the cost of the integrated circuit chip and the majority of device failures are generally packaging related.
The integrated circuit should be packaged in a suitable medium that will protect it in subsequent manufacturing steps and from the environment of its intended application. Wire bonding and encapsulation are the two main steps in the packaging process. Wire bonding connects the leads from the chip to the terminals of the package. The terminals allow the integrated circuit package to be connected to other components. Following wire bonding, encapsulation is employed to seal the surfaces from moisture and contamination and to protect the wire bonding and other components from corrosion and mechanical shock.
Conventionally, the packaging of integrated circuits has involved attaching an individual chip to a lead frame, where, following wire bonding and encapsulation, designated parts of the lead frame become the terminals of the package. The packaging of integrated circuits has also involved the placement of chips on a surface where, following adhesion of the chip to the surface and wire bonding, an encapsulant is placed over the chip to seal and protect the chip and other components.
The use of ball grid arrays (BGAs) to package electronic circuits and devices such as semiconductor dies or integrated circuit chips is becoming more prevalent. BGA packaging has proven to provide substantial advantages over other packaging techniques such as, for example, dual in-line packages (DIPs), pin grid array (PGA) packages, tape carrier packages (TCPs), and quad flat packs (QFPs). The advantages of BGA packaging become especially significant when used to package dies or chips having a high pin count and when used to package devices employing high frequency signals. BGA packaging provides the additional advantage of being able to use conventional surface mount technologies (SMTs) and assembly techniques when mounting BGA packages to a printed circuit board (PCB).
A BGA package generally includes a die or chip, multiple substrate layers, and a heat spreader. The die is generally mounted on the heat spreader/stiffener using a thermally conductive adhesive or glue, such as an epoxy. One of the substrate layers includes a signal plane that provides various signal lines or traces that can be coupled to a corresponding die bond pad using a wire bond. The signal traces are then coupled with a solder ball at the other end. As a result, an array of solder balls is formed so that the BGA package may be electrically and mechanically coupled to other circuitry, generally through a PCB, using the array of solder balls that is referred to as a ball grid array.
BRIEF SUMMARY OF THE INVENTION
A micro ball grid array (micro-BGA) substrate has numerous metal traces formed thereon and/or therein. Such traces electrically couple terminals on a first side of the substrate to ball shaped contacts on a second side of the substrate. A semiconductor chip, which may comprise numerous transistor circuits, is usually affixed to the substrate by a layer of epoxy. Hence, in such case, the epoxy bonds to the chip and to the first side of the substrate. The epoxy layer over the traces, as well as the composite structure formed with the traces sandwiched therein, helps strengthen the trace structure. However, the epoxy layer often does not cover 100% of the traces. As a result, the portions of the traces without epoxy thereon tend to be weaker than those with the epoxy thereon. Also, because the substrate is not bonded to the chip at the portions without epoxy, such portions may experience more flexing and/or elongation. The inventors of the present invention have found that trace cracks tend to develop where there is no epoxy, and typically at the epoxy boundary. Such trace cracks often cause a discontinuity that prevents electrical current from traveling along the trace as intended. In one aspect, the present invention provides a way to reduce or eliminate the occurrence of such trace cracking.
In accordance with one aspect of the present invention, a packaged semiconductor device is provided. The device comprises a semiconductor chip and a package substrate. The semiconductor chip includes a plurality of conductive pads. A plurality of transistor circuits are formed upon the semiconductor chip. The package substrate has first and second sides. A plurality of conductive terminals are formed on the first side of the package substrate. At least one of the terminals is electrically coupled to at least one of the conductive pads. A plurality of contacts are formed on the second side of the package substrate. A plurality of traces are disposed on the first side of the package substrate. Each trace provides at least part of an electrical coupling between at least one of the terminals and at least one of the contacts. The traces are formed from a metal having a tensile strength of more than about 60 kg per mm
2
. The metal of the traces is preferably a copper based material.
The contacts may be arranged in an array, and the array may be generally configured in a square grid. The contacts on the package substrate may be arranged in a micro ball grid array within a generally square area having dimensions between about 3 mm by 3 mm and about 23 mm by 23 mm. The generally square area for the contacts is often dictated by the dimensions of the chip installed on the package by allowing a maximum spacing on each side of the chip of about 0.35 mm to the solder mask edge, which bounds the area of the contacts. Thus for a 9.3 mm by 9.3 mm chip, for example, with a 0.35 package border allowance around the chip, the area of the contacts is about 10 mm by 10 mm. The package substrate may be generally planar shaped with the first side facing an opposite direction with respect to the second side. The device may further comprise an epoxy layer between the chip and the substrate such that the epoxy layer is bonded to the chip and the substrate to, among other things, affix the chip to the substrate. The substrate may be a flex tape substrate, which may comprise a polyimide material, for example. In alternative, the substrate may be a rigid laminate substrate, which may comprise a bismaleimide-triazine resin (BT-resin), flame retardant fiberglass composite substrate board (e.g., FR-4), and/or a ceramic substrate material. The metal of the traces also may have a percent elongation of at least about 7% at room temperature and/or a percent elongation of at least about 7% at 180° C.
In accordance with another aspect of the present invention, a semiconductor device having a micro ball grid array package is provided. The device comprises an integrated circuit chip and a micro ball grid array package substrate. The integrated circuit chip comprises a plurality of conductive pads and a plurality of transistor circuits. At least some of the conductive pads are electrically coupled to at least some of the transistor circuits. The micro ball grid array package substrate has a first side and a second side. A plurality of conductive terminals are formed on the first side of the micro ball grid array package substrate. At least one of the terminals of the micro ball grid array package substrate is electrically coupled to at least one of the conductive pads of the integrated circuit chip. An array of generally ball-shaped contacts is formed on the second side of the micro ball grid array package substrate. A plurality of traces are formed on the first side of the pack
Arabe Ferdinand B.
Mandapat Ma Celine R.
Perez Paul Gabriel D.
Soria Alvin O.
Brady III Wade James
Huynh Andy
Nelms David
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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