Electricity: conductors and insulators – Conduits – cables or conductors – Preformed panel circuit arrangement
Reexamination Certificate
1999-02-09
2001-02-20
Gaffin, Jeffrey (Department: 2841)
Electricity: conductors and insulators
Conduits, cables or conductors
Preformed panel circuit arrangement
C361S783000, C029S841000
Reexamination Certificate
active
06191370
ABSTRACT:
This application claims the benefit of Korean Application Number 20097/1998 filed May 30, 1998, which is hereby incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a ball grid array (BGA) semiconductor package and a method of fabricating the same. Although the present invention is suitable for a wide scope of applications, it is particularly suitable for increasing a mounting density in a stackable BGA semiconductor package.
2. Discussion of the Related Art
As a semiconductor device becomes increasingly smaller, thinner, and lighter, a high-density semiconductor package has been widely studied to mount more semiconductor chips in one package. A stacked TSOP (thin small outline package) has been used to mount a high capacity semiconductor chip since it has a thickness about one half of a related BGA semiconductor package.
The related BGA package has a wide lead pitch and a resistance to an external lead from an external impact. Also, a mass production is readily realized with this type of BGA package. However, a stackable package can not be fabricated using the structure of the related BGA package.
FIG. 1
is a cross-sectional view illustrating the structure of the related BGA semiconductor package. As shown therein, the BGA semiconductor package includes a substrate
1
having a plurality of through holes
3
. Interconnection portions
5
are formed on upper and lower surfaces of the substrate in a predetermined pattern and filled into the through holes
3
. A is semiconductor chip
7
is attached on a center portion of the upper surface of the substrate
1
. A plurality of wires
9
connecting a plurality of pads (not shown) are formed on one side surface of the semiconductor chip
7
. The interconnection portions
5
are also formed on the upper surface of the substrate
1
. A solder resist
11
covers the upper and lower surfaces of the substrate
1
and the portions of the upper and lower surfaces of the interconnection portions
5
. A molding body
13
is embedding the semiconductor chip
7
and the wires
9
, and a plurality of solder balls
15
are respectively connected with the lower ends of the interconnection wires
5
.
In the above related BGA package, it is impossible to fabricate a stackable package by stacking a plurality of BGA packages since the solder balls are formed on the lower surface of the substrate due to its design limitations. In addition, the above BGA semiconductor package has a lower mounting density compared to other stackable packages having the identical mounting area.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a BGA semiconductor package and a method of fabricating the same that substantially obviate one or more of the problems due to limitations and disadvantages of the related art. Another object of the present invention to provide a BGA semiconductor package and a method of fabricating the same which are capable of fabricating a stackable BGA semiconductor package having a high mounting density.
Additional features and advantages of the invention will be set forth in the description which follows and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other above objects, there is provided a BGA semiconductor package which includes a lower substrate including an insulation substrate having a predetermined-shaped recess formed on a center upper surface of the same, a plurality of lower through holes, each of said lower through holes having an upper entrance portion having a larger diameter compared to that of a lower entrance portion and being formed on the insulation substrate except on the recess, and a plurality of predetermined-shaped conductive wiring portions formed on an upper surface of the insulation substrate, a semiconductor chip mounted on the recess by an adhesive, wires connecting the wiring portions and a plurality of pads, an encapsulating member encapsulating the wires, the semiconductor chip and the recess; a plurality of conductive balls each placed on a corresponding one of the lower through holes, and an upper substrate including a through portion formed on a portion corresponding to the encapsulating member, and a plurality of upper through holes, each of said upper through holes being formed at a portion corresponding to a corresponding one of the conductive balls and having an upper entrance portion narrower than the lower entrance portion, whereby the upper substrate is stackable on the lower substrate.
In another aspect of the present invention, a BGA semiconductor package fabrication method includes the steps of preparing a lower substrate having an insulation substrate having a recess formed at a center portion of the same, a plurality of lower insulation substrates formed on the insulation substrate except for the recess and having an upper portion wider than a lower portion and a conductive wiring portion formed on the upper surface of the insulation substrate, attaching a semiconductor chip on the recess, wiring the pads of the semiconductor chip to the wiring portions using a wire, encapsulating the semiconductor chip, the wire and the recess using an encapsulating member, mounting conductive balls on the lower through holes, and bonding a frame type upper substrate having through holes formed at a center portion of the same and a lower substrate wherein upper through holes each have an upper portion of the same wider than a lower portion of the same, and the upper through holes are formed to correspond with the lower through holes.
In another aspect of the present invention, a ball grid array semiconductor package includes a first substrate having a plurality of first holes and a recess, a second substrate having a plurality of second holes and a third hole, a plurality of conductive balls connecting the first and second substrates by filling the first and second holes, a semiconductor chip on the recess of the first substrate, a first conductive wiring portion electrically connecting the semiconductor chip and the conductive balls, and an encapsulating member encapsulating the semiconductor chip.
In another aspect of the present invention, a stackable ball grid array semiconductor package includes a first substrate having a plurality of first holes and a first recess, a second substrate having a plurality of second holes and a third hole, a plurality of first conductive balls filling the first and second holes, a first semiconductor chip on the first recess, a first conductive wiring portion electrically connecting the first semiconductor chip and the first conductive balls, a first encapsulating member encapsulating the first semiconductor chip, a third substrate having a plurality of fourth holes and a second recess, a fourth substrate having a plurality of fifth holes and sixth a hole, a plurality of second conductive balls filling the first and second holes, the first and second conductive balls being electrically connected each other, a second semiconductor chip on the second recess, a third conductive wiring portion electrically connecting the second semiconductor chip and the second conductive balls, and a second encapsulating member encapsulating the second semiconductor chip.
In a further aspect of the present invention, a method of fabricating a ball grid array semiconductor package, the method comprising the steps of preparing first and second substrates, the first substrate having a plurality of first holes and a first recess, and the second substrate having a plurality of second holes and a third hole, attaching a first semiconductor chip on the first recess of the first substrate, electrically connecting the first semiconductor chip to a first conductive wiring portion, encapsulating the f
Gaffin Jeffrey
LG Semicon Co. Ltd.
Morgan & Lewis & Bockius, LLP
Norris Jeremy
LandOfFree
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