Active solid-state devices (e.g. – transistors – solid-state diode – With means to control surface effects – Insulating coating
Reexamination Certificate
1998-09-04
2001-12-04
Williams, Alexander O. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
With means to control surface effects
Insulating coating
C257S528000, C257S536000, C257S537000, C257S738000, C257S778000, C257S775000, C257S533000, C257S532000, C257S774000, C257S421000, C257S737000, C257S723000, C338S320000, C338S309000, C338S329000
Reexamination Certificate
active
06326677
ABSTRACT:
BACKGROUND OF THE PREFERRED EMBODIMENT(S)
1. Field of the Preferred Embodiment(s)
This invention generally relates to resistors for electronics. Specifically, the invention is a group of resistors mounted in a high density network or array package using spherical solder connections.
2. Description of the Related Art
Resistor networks are commonly used to terminate high speed digital signal lines to minimize unwanted reflections back through the transmission structure which is typically a printed circuit board. In most applications, the terminations are made by placing a resistor with a resistance matching the impedance of the transmission line, at the end of the transmission line. One end of the resistor is connected to a common termination voltage and the other end is connected to the signal line. For these applications, a bussed resistor network is a convenient solution, since one end of the termination is common to all signal lines.
The previous resistor network designs include surface mount, and through hole SIP and DIP versions.
Despite the advantages of each type of prior art resistor network, none have been easily or economically manufactured with a high density of interconnects per unit area on a printed circuit board. In particular, providing the electrical connections only on the periphery of the resistor network causes the electrical leads to be tightly spaced on the edge of the device, while the area in the interior of the device is unused for electrical interconnections.
Therefore, there is a current unmet and heretofore long felt need for a resistor network with higher density, low cross-talk noise and improved signal integrity.
DESCRIPTION OF RELATED ART
Examples of patents related to the present invention are as follows, and each patent is herein incorporated by reference for the supporting teachings:
U.S. Pat. No. 4,945,399, is an electronic package with integrated distributed decoupling capacitors.
U.S. Pat. No. 5,557,502, is a ball grid array package.
U.S. Pat. No. 4,300,115, is a multi-layer via resistor.
U.S. Pat. No. 4,658,234, is a resistor network.
U.S. Pat. No. 5,621,619, is an all ceramic surface mount sip and dip network having spacers and solder barriers.
U.S. Pat. No. 5,379,190, is a chip type composite electronic part.
U.S. Pat. No. 4,332,341, is a fabrication of circuit packages using solid phase solder bonding.
U.S. Pat. No. 5,539,186, is a temperature controlled multi-layer module.
U.S. Pat. No. 5,216,404, is a SIC thin film thermistor.
U.S. Pat. No. 4,654,628, is a network resistor unit.
U.S. Pat. No. 5,661,450, is a low inductance termination resistor array.
The foregoing patents reflect the state of the art of which the applicant is aware and are tendered with the view toward discharging applicant's acknowledged duty of candor in disclosing information that may be pertinent in the examination of this application. It is respectfully stipulated, however, that none of these patents teach or render obvious, singly or when considered in combination, applicant's claimed invention.
SUMMARY OF THE PREFERRED EMBODIMENT(S)
It is a feature of the invention to provide a ball grid array resistor network. Specifically, there is a substrate, several resistors, conductors, and vias arranged in a configuration. Solder spheres are used to connect the resistors to other electronic circuitry such as a printed circuit board.
It is a feature of the invention to provide a ball grid array resistor network including a substrate that has top and bottom surfaces. Resistors are disposed on the top surface. Conductors are disposed on the top surface, and each conductor is electrically connected to an end of each resistor. Vias extend through the substrate and are electrically connected to the conductors. Solder spheres are disposed on the bottom surface, and are electrically connected to the vias. A cover coat is disposed over the conductors and resistors.
It is a feature of the invention to provide a ball grid array resistor network which has a substrate with a bottom surface. Resistors are disposed on the bottom. Conductors are disposed on the bottom surface and each conductor is electrically connected to an end of each of the resistors. A glass cover coat having several apertures is disposed over the resistors, conductors and the bottom surface. The apertures are aligned with the conductors. Solder spheres are disposed at least partially in the apertures and are electrically connected to the conductors.
The invention resides not in any one of these features per se, but rather in the particular combination of all of them herein disclosed and claimed and it is distinguished from the prior art in this combination of all of its structures for the functions specified.
There has thus been outlined, rather broadly, the more important features of the invention so that the detailed description thereof that follows may be better understood, and so that the present contribution to the art may be better appreciated. There are, of course, additional features of the invention that will be described hereinafter and which will form the subject matter of the appended claims. Those skilled in the art will appreciate that the preferred embodiment may readily be used as a basis for the designing of other structures, methods and systems for carrying out the several purposes of the present invention. It is important, therefore, that the claims are regarded as including such equivalent constructions since they do not depart from the spirit and scope of the present invention.
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Bloom Terry R.
Burry Stephen W.
Seffernick Lewis L.
Vandenboom Robert M.
Zdanys, Jr. John
Borgman Mark W.
Bourgeois Mark P.
CTS Corporation
Watkins Albert W.
Williams Alexander O.
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