Ball grid array package stack

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Bump leads

Reexamination Certificate

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Details

C257S686000, C438S107000, C361S704000

Reexamination Certificate

active

07071555

ABSTRACT:
Disclosed herein is a ball grid array (BGA) package stack that is not limited by ball arrangement because it utilizes a foldable circuit substrate, which permits interconnection between upper and lower individual BGA packages. The foldable circuit substrate has three portions. By bending the middle second portion, the foldable circuit substrate is folded in two. In the lower BGA package, an IC chip is attached on and electrically connected to a top surface of the first portion, and external connection terminals such as solder balls are formed on a bottom surface of the first portion. The top surface of the first portion is covered with a molding resin to protect the chip, and the third portion is placed on an upper surface of the molding resin. The upper BGA package is constructed in a similar manner to the lower BGA package as described above. For stacking, the interconnection terminals of the upper BGA package are joined and electrically connected to the third portion of the foldable circuit substrate of the lower BGA package.

REFERENCES:
patent: 6014316 (2000-01-01), Eide
patent: 6576493 (2003-06-01), Lin et al.
patent: 6576992 (2003-06-01), Cady et al.
patent: 2002/0044423 (2002-04-01), Primavera et al.
patent: 2003/0168725 (2003-09-01), Warner et al.
patent: 2001-11310 (2001-02-01), None
patent: 2001-78288 (2001-08-01), None
patent: 2001-0078288 (2001-08-01), None
English language of Abstract from Korean Patent Publication No. 2001-11310, filed Feb. 15, 2001.
English language abstract of Korean Publication No. 2001-0078288.
English language abstract of Korean Publication No. 2001-78288.

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