Ball grid array package for high speed devices

Details Ball grid array package for high speed devices Ball grid array package for high speed devices

2003-07-01

2004-07-13

Potter, Roy (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C257S759000, C438S622000, C438S623000

Reexamination Certificate

active

06762498

ABSTRACT:

FIELD OF THE INVENTION
The present invention is related in general to the field of electronic systems and semiconductor devices and more specifically to the field of high speed integrated circuits in ball grid array packages.
DESCRIPTION OF THE RELATED ART
Ball Grid Array (BGA) packages have emerged as an excellent packaging solution for integrated circuit (IC) chips with high input/output (I/O) count. A BGA device generally includes an IC chip mounted on a substrate (frequently via a heat spreader) and usually encapsulated. Typical BGA packages use sheet-like substrates with I/O terminals on both surfaces and solder balls for surface mount connection to the external parts (such as printed circuit boards, PCB). In most devices, the substrates are composites of metal layers alternating with insulating layers, for instance, copper-laminated resin substrates.
In typical BGAs, one of the substrate layers includes a signal plane that provides various signal traces, which can be coupled on one end to a corresponding chip bond pad using wire bond or reflow connections. On the other end, the signal lines are coupled by solder connections to external parts and circuitry. Additionally, a ground plane will generally be included on one of the substrate layers to serve as an electrically active ground plane for improving overall device performance: lowering the inductance, providing controlled impedance, and reducing cross talk. These features become the more important the higher the BGA pin count is.
When a BGA package is used for high speed signals, the electrical performance requirements drive the need to use multi-layer substrates. As an example, for high speed digital signal processors (DSP) and mixed signal products (MSP), the package consists of four or more layers for routing. Typically, two of these routing layers are power and ground planes, which may be positioned next to the surfaces of the substrate. For high speed applications, the distance between signal and power or ground layers may only be 30 to 50 &mgr;m.
As clock frequencies and current levels increase in semiconductor devices, prevailing solutions of BGA packages are lagging in the ability to provide acceptable signal transmission, maintain signal integrity, and provide stable power and ground supplies. As a typical example, when the I/O terminal pitch is required to be 1 mm, the terminal pad area is about 700 &mgr;m diameter, and the solder ball after reflow will also be about 700 &mgr;m diameter. The terminal pad acts as a capacitor to the nearest power or ground plane. This capacitance is on the order of 450 to 600 fF. At a signal frequency of 1 GHz, this capacitance represents an impedance of around 400 &OHgr; to ground; at 3 GHz, it is about 133 &OHgr; to ground. In both cases, this impedance represents a significant impedance discontinuity and generates a reflection coefficient of around 15 dB.
In order to reduce this reflection coefficient, high speed designers have resorted to the method of removing the portion of the ground/power plane directly adjacent to the I/O pad. This radical action reduces the capacitance of the pad to the ground/power plane; for example, removing the plane area opposite the pad will reduce the capacitance by approximately a factor of two. At the same time, however, this hole weakens the mechanical stability of the substrate; it can initiate warpage and cause eventual delamination of the substrate.
A need has therefore arisen to break this vicious cycle and conceive a concept for reducing the signal reflection without endangering the mechanical stability of the substrate. Preferably, this structure should be based on a fundamental design concept flexible enough to be applied for different semiconductor product families, BGA structures, and a wide spectrum of design and assembly variations. It should not only meet high electrical and thermal performance requirements, but should also achieve improvements towards the goals of enhanced process yields and device reliability. Preferably, these innovations should be accomplished using the installed equipment base so that no investment in new manufacturing machines is needed.
SUMMARY OF THE INVENTION
One embodiment of the invention is a substrate for use in semiconductor devices, having first and second surfaces and a base structure made of insulating material. A plurality of I/O terminal pads is distributed on the first and second surfaces, and these terminal pads are interconnected by conducting traces integral to the base structure. A plurality of selected metal layers is distributed in the structure; the metal layers are substantially, parallel to the surfaces and separated by the insulating material from each other and from the surfaces. At least one metal layer opposite each of the surfaces has openings therein configured so that the metal areas directly opposite each of the terminal pads are electrically isolated from the remainder of the layer. The width of these openings is selected to provide a pre-determined capacitance between each of the terminals and the remainder of the metal layer.
Another embodiment of the invention aims at semiconductor devices, which have an integrated circuit chip with contact pads and a substrate with first and second surfaces and a base structure made of insulating material. A plurality of selected metal layers is distributed in the structure; the metal layers are substantially parallel to the surfaces and separated by insulating material from each other and from the surfaces. At least one metal layer opposite each of the surfaces has openings therein configured so that the metal areas directly opposite each of the terminal pads are electrically isolated from the remainder of the layer. The chip contact pads are connected to the plurality of substrate terminal pads on the first surface, respectively. The terminal pads on the second surface operate as external device terminals having predetermined capacitance.
In both of the embodiments described above, the capacitance of the, terminal pads is determined as the series sum of the capacitive contributions from the isolated area and the opening.
Embodiments of the present invention are related to high pin count, high frequency integrated circuit devices intended for high speed and high power. It is a technical advantage that good electrical match of the high speed input pad to the device can be achieved, which practically eliminates the signal reflection, while the mechanical reliability of the package remains high. The original metallization in the package substrate is almost fully preserved, so that the possibility for warpage due to large metallization gaps in substrate metal layers is avoided. One or more embodiments of the invention offer choices relative to the magnitude of the impedance matching structure and the materials and processes chosen; for the connection to the IC chip, both wire bonding and solder reflow are acceptable.
The technical advances represented by certain embodiments of the invention will become apparent from the following description of the preferred embodiments of the invention, when considered in conjunction with the accompanying drawings and the novel features set forth in the appended claims.

Affiliated with

Also associated with

Rating

Ball grid array package for high speed devices does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Ball grid array package for high speed devices, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Ball grid array package for high speed devices will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3244788