Electricity: conductors and insulators – Conduits – cables or conductors – Preformed panel circuit arrangement
Reexamination Certificate
1999-04-05
2001-05-29
Gaffin, Jeffrey (Department: 2841)
Electricity: conductors and insulators
Conduits, cables or conductors
Preformed panel circuit arrangement
C174S255000, C257S678000, C257S690000, C361S760000, C361S752000, C361S756000
Reexamination Certificate
active
06239383
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 87114763, filed Sep. 5, 1998, the full disclosure of which is incororated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a ball-grid array (BGA) IC packaging frame, and in particular to a ball-grid array IC packaging frame having supporting pads for preventing non-contact soldering and short circuits.
2. Description of the Related Art
A ball-grid array (BGA) IC packaging, a novel IC packaging with a large number of pins, is suitable for sub-micron ultra-large scale integrated circuits. The more complicated the functions of ICs, the higher the integration of transistor-based ICs. Generally, the conventional quad flat pack (QFP) and pin-grid array (PGA), which commonly only provide about 100-200 pins for each packaging, cannot handle with current complicated digital logic ICs. That is, the QFP and PGA cannot meet practical requirements at all.
Today, 64-bit microprocessor-based personal computers (PCs) have been widely utilized. The core logic circuits of a PC are electrically connected to a microprocessor, DRAMs serving as main memories and SRAMs serving as fast access memories thereof by a 64-bit bus. When the core logic circuits are manufactured into an IC chip, at least approximate 200 pins are required for a data bus and a address bus. If other control signals are taken into consideration, the total number of pins required are easily over 300. In this case, the BGA IC packaging can meet the requirement for a large number of pins.
A ball-grid array packaging substrate is constituted by a small-size printed circuit board (PCB) based on a printed circuit technique. As known by those skilled in the art, a die is automatically mounted on the substrate by a pick-and-place machine after wafer sawing. Then, the bonding pads of the dice are connected to the corresponding IO pads of the substrate with wires by a wire-bonding machine. Next, the die including the bonding pads and IO pads is encapsulated with a plastic molding compound by a molding machine. After the plastic cools, a solder reflow treatment is performed to form several hundreds of tin balls on the rear surface of the substrate. Since logic circuits contained in a current IC have more various functions and the operating frequency thereof already reaches several hundreds of MHz, more number of IO pads and shorter lengths of wires between a die and pines are required to perform IC packaging. Accordingly, the BGA IC packaging has been mainly and widely utilized for packaging high-integration and high-speed ICs in recent years. The BGA IC packaging has the following advantages.
(1) More IO pads can be provided.
(2) IC packages having small sizes are suitable for small-size equipment, such as notebooks.
(3) Ground bounce is greatly reduced, especially for high-speed circuits due to small inductance between induced by shorter wires.
(4) Tin balls are utilized to electrically connect a PCB, instead of conventional lead pins. Therefore, the problem of pins bent or shifted during delivery can be completely eliminated.
However, several disadvantages exist in the BGA IC packaging. Referring to
FIG. 1
, a bottom view of a BGA IC package
10
according to the prior art is shown. A plurality of ball-grid array tin balls
14
is formed on the rear surface of the conventional BGA IC package
10
. Since the BGA IC package
10
is used in coordination with surface-mount technology (hereinafter referred to as SMT) where tin balls are utilized for connection with a PCB instead of pins, requirements for packaging become stricter. The SMT is a method to mount a BGA IC chip on a PCB. Then, a nitrogen solder reflow treatment is performed to melt the tin balls
14
beneath the BGA IC package
10
, making the BGA IC and PCB knitted together to form a functional system. At this time, if the temperature-time curve of the nitrogen solder reflow treatment is not well-controlled, a short circuit between two adjacent tin balls as shown in
FIG. 2
or non-contact soldering as shown in
FIG. 3
will occur.
Referring to
FIG. 4
, a poor contact between a BGA IC
16
and a PCB
18
is shown. can be obviously seen from
FIG. 4
, non-contact soldering
20
and a short circuit
22
occur on a first end and a second end of the BGA IC
16
where the first end is higher than the second end, because of having no supports, such as pins in PGA, to support the BGA IC
16
. This is a disadvantage of the BGA IC packaging.
Further more, in the SMT, the BGA IC
16
is mounted on the PCB
18
thereby to allow tin balls beneath the BGA IC
16
to connect corresponding tin solders which was spread on the surface of the PCB pads. How ever, the tin solders on the PCB will be dissipated if the BGA IC
16
is placed down from a higher position or the tin solders are easily squeezed if the BGA IC
16
is placed down form a lower position. Either will put the tin solders on the PCB in an inappropriate collapsed soldering condition, resulting in short circuits or non-contact soldering. Moreover, the PCB is easily warped by heat, causing being unable to be stably placed. This results in a poor yield.
SUMMARY OF THE INVENTION
In view of the above, an object of the invention is to provide a ball-grid array (BGA) IC packaging frame for preventing non-contact soldering and short circuits. To attain the above-stated object, in a ball-grid array IC packaging frame according to the invention, a plurality of supports are formed on the rear surface of a BGA IC package where tin balls are located. As a result, a BGA IC packaged according to the invention does not have its one end higher than the other end when mounted on a PCB. Thus, non-contact soldering and short circuits can be completely prevented.
The ball-grid array IC packaging frame of the invention includes a plurality of ball-grid array tin balls formed on the rear surface of a ball-grid array IC package and a plurality of supporting pads formed on the surrounding of the rear surface of the ball-grid array IC packages.
REFERENCES:
patent: 5477933 (1995-12-01), Nguyen
patent: 5598036 (1997-01-01), Ho
patent: 5641946 (1997-06-01), Shim
patent: 5662725 (1997-09-01), Moore et al.
patent: 5716222 (1998-02-01), Murphy
patent: 5724728 (1998-03-01), Bond et al.
patent: 5751556 (1998-05-01), Butler et al.
patent: 5760469 (1998-06-01), Higashiguchi et al.
patent: 5985695 (1999-11-01), Freyman et al.
patent: 6014318 (2000-01-01), Takeda
Gaffin Jeffrey
Huang Jiawei
J. C. Patents
Patel I B
VIA Technologies Inc.
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