Ball grid array having reduced mechanical stress

Details Ball grid array having reduced mechanical stress Ball grid array having reduced mechanical stress

1995-06-15

1997-01-28

Saadat, Mahshid D.

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Bump leads

257673, 257690, 257692, 257737, 257780, 257786, H01L 2358, H01L 2348, H01L 2352

Patent

active

055980368

ABSTRACT:
A semiconductor package, including semiconductor dies, a ball grid array, and a printed circuit board, is described. Said package has been designed with a view to minimizing its level of internal mechanical stress. This has been achieved through use of two sets of solder joints that have different melting points. The joints with the higher melting point are positioned in the region, on the ball grid array, where it is known that stress will be a maximum in the finished package. The lower melting point joints occupy the remaining positions on the underside of the ball grid array. Ball grid array and printed circuit board are attached to one another by heating at a temperature that is between the aforementioned two melting points.

REFERENCES:
patent: 4807021 (1989-02-01), Okumura
patent: 4918514 (1990-04-01), Matsuda et al.
patent: 5214308 (1993-05-01), Nishiguchi et al.
patent: 5216278 (1993-06-01), Lin et al.
patent: 5220200 (1993-06-01), Blanton
patent: 5233504 (1993-08-01), Melton et al.
patent: 5250848 (1993-10-01), Christie et al.
patent: 5334857 (1994-08-01), Mennitt et al.

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