Ball grid array configuration for reducing path distances

Details Ball grid array configuration for reducing path distances Ball grid array configuration for reducing path distances

2005-04-27

2009-12-15

Reichard, Dean A. (Department: 2841)

Electricity: electrical systems and devices

Housing or mounting assemblies with diverse electrical...

For electronic systems and devices

C361S764000

Reexamination Certificate

active

07633764

ABSTRACT:
Presented herein are ball grid array configurations for reducing path distances. In an exemplary embodiment, there is presented a memory system. The memory system comprises a printed circuit board, a memory controller, and a memory. The printed circuit board comprises a first layer and a second layer. The memory controller comprises a first plurality of pins connected to the first layer and a second plurality of pins connected to the second layer. The memory comprises a first plurality of pins connected to the first layer and a second plurality of pins connected to the second layer. The first layer comprises a plurality of connection paths connecting the first plurality of pins of the memory to the first plurality of pins of the memory controller. The second layer comprises a plurality of connection paths connecting the second plurality of pins of the memory to the second plurality of pins of the memory controller.

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patent: 2002/0156538 (2002-10-01), Chang
patent: 3123620 (1983-01-01), None
patent: 3123620 (1983-01-01), None

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