Ball grid array casing for integrated circuits

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified configuration

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257778, 257779, 257787, H01L 2348

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active

057367892

ABSTRACT:
An integrated circuit casing includes an insulating plate having metallized through holes connected to conductive tracks. The conductive tracks on the lower surface extend to first pads which are designed to receive connection balls. The conductive tracks of the upper surface extend to second pads connected to terminals of an integrated circuit chip. The chip is glued on the upper surface of the plate. An encapsulation material embeds the chip. A first insulating layer is deposited on the lower surface of the plate and etched away in front of the first pads. A second insulating layer is deposited on the upper surface of the plate and etched away in front of the second pads and the through holes, the encapsulation material filling the holes.

REFERENCES:
patent: 5151771 (1992-09-01), Hiroi et al.
patent: 5216278 (1993-06-01), Lin et al.
patent: 5218234 (1993-06-01), Thompson et al.
patent: 5355283 (1994-10-01), Marrs et al.
patent: 5400220 (1995-03-01), Swamy
French Search Report from French Patent Application No. 94 09490, filed Jul. 26, 1994.
Patent Abstracts of Japan, vol. 18, No. 364 (E-1575) Jul. 8, 1994 & JP-A-06 097 666 Hitachi, Ltd.
Patent Abstract of Japan, vol. 14, No. 190 (E-0918) Apr. 18, 1990 & JP-A-02 037 761 NEC Corp.

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