Ball assignment for ball grid array package

Details Ball assignment for ball grid array package Ball assignment for ball grid array package

2001-04-27

2004-07-13

Cuneo, Kamand (Department: 2827)

Electricity: conductors and insulators

Conduits, cables or conductors

Preformed panel circuit arrangement

C174S255000, C174S262000, C361S792000, C361S803000

Reexamination Certificate

active

06762366

ABSTRACT:

FIELD
This invention relates to the field of microelectronic circuitry fabrication. More particularly the invention relates to a system for assigning ball placements for a ball grid array package and routing the contacts with an associated printed circuit board.
BACKGROUND
As microelectronic devices get increasingly smaller, new problems with fabricating the devices appear. For example, as the device sizes decrease, an increasingly greater number of contacts to the device need to be made within an increasingly smaller contact area. The number of contacts within a given surface area of an integrated circuit is generally referred to as the contact density. Obviously, as the contact density of the integrated circuit increases, so to will the contact density of the associated packaging for the integrated circuit tend to increase.
This situation of increasing contact density tends to create difficulties in providing the number of contacts required in a manner where signal integrity through the contacts is maintained. Further, routing the signals through the contacts to the package presents additional challenges as the contact density increases.
What is needed, therefore, is a ball assignment for a ball grid array package and an associating routing structure for an associated printed circuit board that is capable of handling the high contact count within a relatively limited contact area and in a manner where signal integrity is maintained.
SUMMARY
The above and other needs are met by a printed circuit board having contacts in a contact array of rows and columns. Groups of n columns of the contacts are electrically connected to n−1 columns of vias disposed interstitially in a via array between the n columns of the contacts. A major vertical routing channel is formed between adjacent groups of n columns of the contacts and the n−1 columns of vias. First electrical traces are electrically connected to a first number of the vias. The first electrical traces are routed to an outside edge of the via array through the major vertical routing channel.
Thus, by grouping the contact connections to a smaller number of vias, and thereby creating the major vertical routing channel, a greater number of traces can be routed out of the via array through the open space provided by the major vertical routing channel. In this manner a greater number of traces can be routed out on each layer of the printed circuit board, and fewer layers of the printed circuit board are required for routing out the contacts.


REFERENCES:
patent: 3605063 (1971-09-01), Stewart
patent: 6194668 (2001-02-01), Horiuchi et al.
patent: 6198635 (2001-03-01), Shenoy et al.
patent: 6271478 (2001-08-01), Horiuchi et al.
patent: 6388890 (2002-05-01), Kwong et al.
patent: 6407344 (2002-06-01), Horiuchi et al.

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